Block Diagram - Audio/Camera Section - Sony mz-dh10p Service Manual

MZ-DH10P
6-2. BLOCK DIAGRAM – AUDIO/CAMERA Section –
CAMERA
MODULE
D_SO
D_SI
D_SCK
C_ACK
C_NACK
BZ1
C_REQ
D_ACK
D_NACK
D_REQ
WAKE
RESET
LI_BAT
FLASH MEMORY
IC802
XCE 37
XOE 38
40
XWE
XRESET 42
RESET SIGANL RESET
M_F_VDD GENRATOR SWITCH
IC803 Q804
XRST
(Page 23)
B
XWK1, XWK2,
XWK4
(Page 23) C
MZ-DH10P
BEEP 199
DCLSOUTL
151
FROM IC801 (1/3)
(MD SERVO SECTION)
DCLSOUTR
150
FS512 312
285 SO4
D_EN2 229
284 SI4
D_EN1 228
286 SCK4
D_ENREG 211
295 CAMERA_ACK
D_VCONT_PWM 243
293 CAMERA_NACK
294 CAMERA_REQ
292 DRIVE_ACK
XMUTE 212
290 DRIVE_NACK
291 DRIVE_REQ
289 WAKE
DTCK 313
287 RESET
RMC_KEY 131
CM B+
UDP 314
UPUEN 318
UDM 315
378 EBCS0
384 EBRD
385 EBWE
X801
48MHz
319
WAKE UP SWITCH
193 USB_WAKE
Q803
133 124 125 248 249 103
D301
D501
ROTARY
S301
ENCODER
DOWNLOAD
S101
(JOG)
S102 – 106,
S201, 202,
S303, 304
D101
OPR
(RED)
SWITCHING DRIVER,
HEADPHONE AMP
IC351
OUT_
2 BEEP_IN 17
BEEP2
OUT2
3 DIN2 15
MUTING
Q351
OUT1
4 DIN1 7
OUT_BEEP1 5
23 MCK
26 EN2
MUTING
25 EN1
Q151, 251
27 ENREG
11 VCONT
MUTING
CONTROL
Q352
CN451 (1/2)
(USB)
6
DATA+
5
DATA–
X872
32.768kHz
X802
22.5792MHz
320 310 311
SYSTEM CONTROLLER, DSP
FLASSH MEMORY CONTROOLER
IC801 (2/3)
288 244 128 132 135 188
D892
LED DRIVE LED DRIVE
Q492 Q405
S895 S892 S893
D102 D103
LENS COVER HALF OPEN/CLOSE
OPR CHG
DETECT LOCK DETECT
(GRN)
22 22
MUTEON
D
J351
i/ LINE OUT
F351
VC1 B+
RVDD
DTCK
KEY_R
RGND
RMC KEY
E
D871
+3.3V
REGULATOR
VB B+
IC872
4
REAL TIME
LEVEL SHIFT
CLOCK
IC873
IC871
8 OSCOUT SIO 1
SCLK 2
7 OSCIN
12
247
SI0 195
SO0 196
SCK0 197
XCS_NV 239
184 253 227
• SIGNAL PATH
–1 –2
S302
S891–1 S891–2
Hi-MD HOLD
PROTECT
PROTECT
DETECT
HOLD
DETECT
OFF
(Page 23)
(Page 23)
EEPROM
IC891
2 SO
5 SI
6 SCK
1 XCS
SDO0, SCK0
F (Page 23)
: PLAYBACK
: USB input from PC
: USB output to PC