Samsung SCX-5315F Service Manual page 123

3-2-3 RISC MICROPROCESSOR
1) RISC MICROCESSOR PIN & INTERFACE(SPGPm)
Ball No Pin No
B1 1
C2 2
D2 3
D3 4
E4 5
C1 6
D1 7
E3 8
E2 9
E1 10
F3 11
G4 12
F2 13
F1 14
G3 15
G2 16
G1 17
H3 18
H2 19
H1 20
J4 21
J3 22
J2 23
J1 24
K2 25
K3 26
K1 27
L1 28
L2 29
L3 30
L4 31
M1 32
M2 33
M3 34
M4 35
N1 36
N2 37
N3 38
P1 39
P2 40
R1 41
P3 42
Samsung Electronics
Pin Name I/O
SD15 I/O
VSS_PLL1 -
VDD_PLL1 -
DATA0 / GPI1 I/O
MCLK
DATA6 / GPI7 I/O
DATA1 / GPI2 I/O
DATA5 / GPI6 I/O
VDD_RING_OSC -
DATA3 / GPI4 I/O
DATA9 / GPI10 I/O
GND -
DATA8 / GPI9 I/O
DATA7 / GPI8 I/O
DATA12 / GPI13 I/O
DATA11 / GPI12 I/O
DATA10 / GPI11 I/O
DATA4 / GPI5 I/O
DATA15 / GPI16 I/O
DATA14 / GPI15 I/O
VDD_CORE -
DATA19 I/O
DATA18 I/O
DATA17 I/O
DATA16 I/O
DATA22 I/O
DATA13 / GPI14 I/O
DATA20 I/O
DATA21 I/O
DATA25 I/O
DATA26 I/O
DATA23 I/O
DATA24 I/O
DATA29 I/O
DATA30 I/O
DATA27 I/O
DATA28 I/O
VDD_ARM -
DATA31 I/O
DATA2 / GPI3 I/O
VDD_CORE -
nROMCS2 O
- This Document can not be used without Samsung's authorization -
Description
SDRAM Bus Data[15]
VSS for Core PLL
VDD for Core PLL (1.8V)
ROM Bus Data[0] / GPI[1]
I Core PLL Clock Input (12MHz)
ROM Bus Data[6] / GPI[7]
ROM Bus Data[1] / GPI[2]
ROM Bus Data[5] / GPI[6]
VDD for Ring Oscillator (1.8V)
ROM Bus Data[3] / GPI[4]
ROM Bus Data[9] / GPI[10]
GROUND_RING
ROM Bus Data[8] / GPI[9]
ROM Bus Data[7] / GPI[8]
ROM Bus Data[12] / GPI[13]
ROM Bus Data[11] / GPI[12]
ROM Bus Data[10] / GPI[11]
ROM Bus Data[4] / GPI[5]
ROM Bus Data[15] / GPI[16]
ROM Bus Data[14] / GPI[15]
VDD for CORE (1.8V)
ROM Bus Data[19]
ROM Bus Data[18]
ROM Bus Data[17]
ROM Bus Data[16]
ROM Bus Data[22]
ROM Bus Data[14] / GPI[14]
ROM Bus Data[20]
ROM Bus Data[21]
ROM Bus Data[25]
ROM Bus Data[26]
ROM Bus Data[23]
ROM Bus Data[24]
ROM Bus Data[29]
ROM Bus Data[30]
ROM Bus Data[27]
ROM Bus Data[28]
VDD for ARM
ROM Bus Data[31]
ROM Bus Data[2] / GPI[3]
VDD for CORE (1.8V)
ROM Bank2 Select_n
Circuit Description
PAD
BD8TARP_TC
-
-
BD8TRP_FT
TLCHT_TC
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
-
BD8TRP_FT
BD8TRP_FT
-
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
-
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
BD8TRP_FT
-
BD8TRP_FT
BD8TRP_FT
-
B4TR_TC
3-3