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MAIN(OP DRV) SCHEMATIC DIAGRAM
TO PARAGON
H_OFFSET
H_GAIN
TO CPU
IRIS_O/C
IRIS_PWM
HALL_A/D
IR_DET
IR_FLICK
8.2K
R4987
Q4981
RPM-22PB
L4901
NQR0602-001X
C4902
1
LENS_LED
TO CPU
F/Z_CS
CAM_OUT
TO CPU,
CDS/TG
CAM_CLK
TO CPU,
T_F_V_RST
VIDEO
TO PARAGON
VD_F/Z
F/Z_MCK
REG_4.8V
TO MDA,
M_REG4.8
REG
REG_3.1V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
1.8K
R4930
C4905
R4911
100p
24K
R4905
1M
7
6
5
4
3
2
8
7
6
5
-
-
-
+
+
+
8
9
10
11
12
13
1
2
3
4
R4981
1.8K
C4903
0.1
R4983
10K
680K
R4903
R4984
22K
330
C4981
1
L4954
10u
NQL38DK-100X
C4951
10
R4970
100
NRSA6AJ-101W
C4956
10/6.3
T
(No.YF123)2-21
C4908
R4918
R4906
R4907
10K
100K
10k
R4917
100p
R4915
68K
1K
R4919
22K
1
1
2
3
4
1
2
-
-
+
+
14
8
7
6
5
8
7
R4933
R4936
10K
33K
R4935
560K
R4938
0
R4904
R4951
1k
R4952
1k
R4953
1k
R4954
1k
R4955
100
L4955
10u
NQL38DK-100X
C4955
C4954
C4953
CH
CH
OPEN
10
OPEN
C4958
C4957
T
OPEN
OPEN
2-22(No.YF123)
0
1
MAIN(OP DRV)
C4916
0.1
3
4
6
5
R4937
1.2K
R4961
270
Q4951
DTC114EE-X
R4956
R4957
4.7
4.7
48
47
46
45
44
43
42
41
40
39
38
37
1 TEST0
C2(W3)
36
2 TEST1
VMC
35
3 TEST2
VSEN_HC
34
4 TEST3
VSEN_LC
33
5 NC
NC
32
IC4951
6 VCC3
NC
31
7 VD
NC
30
AN41902A
8 MCSELECT
NC
29
9 SDATA
VSEN_LB
28
10 SCLK
VSEN
27
11 OSCIN
VMB
26
12 RESET
B2(N4)
25
13 14 15 16 17 18 19 20 21 22 23 24
R4959
R4960
4.7
4.7
yf123_y10575001a_rev1.1
TO MAIN IF(CN4901),CPU
OP_THRMO
F_PTR_AD
Z_PTR_AD
TO MAIN IF(CN4901)
DUMP+
GND
HGVCC+
HGOUT+
HGVSS-
HGOUT-
DUMP-
DRIVE-
DRIVE+
GND
TO MAIN IF
(CN4901),
Z_PTR_AD
CPU
Z_LED
ZOOM02
TO MAIN IF
ZOOM03
(CN4901)
ZOOM04
TO MAIN IF
ZOOM01
(CN4901),
F_PTR_AD
CPU
F_VCC
TO MAIN IF
(CN4901)
TO MAIN IF
OP_THRMO
(CN4901),
GND
CPU
FOCUS02
FOCUS04
TO MAIN IF
(CN4901)
FOCUS01
FOCUS03
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