Main(Cds/Tg) Schematic Diagram - JVC GR-D350UC Schematic Diagrams

MAIN(CDS/TG) SCHEMATIC DIAGRAM

0 1 MAIN(CDS/TG)
TO MAIN IF
(CN4201)
V1
V2
V3
V4
REG_15V
REG_15V
CCD_CTL
RG
SUB
H2
H1
CCD_-7.5V
GND
GND
GND
C4210
CCD_OUT
R4216
0.1
100
GND
GND C4221
10p
GND
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
D4201
1SS355-X
C4206
C4205
C4209 0.1
R4213 1
CDSTG_CS 1
1k
R4214
CAM_OUT
R4215 1k
CAM_CLK 0.1
1
1k
88 63 31 87 62 86 61 28 60 85 27 59 84
18 NC
19 NC
20 NC
22 NC
23 NC
24 NC
25 NC
29 NC
30 NC
32 NC
IC4201
35 NC
LY35174-001A
52 NC
53 NC
56 NC
74 NC
76 NC
77 NC
78 NC
83 NC
89 SUB
90 SUB
91 SUB
92 SUB
1 65 34 2 66 3 67 36 4 37 68 38 39 70 8 40 41 9 71 42 10 72 43
RA4202
100
(No.YF123)2-19
R4201
C4201 100K
µ
1 /25v
TL4202
TL4201
C4203
1
C4212
26 58 57 82 55 81 54 80 21 79
47 µ /6.3v
DVDD2 51
SUBSW 50
VL 5
VM2.4 49
OV4 16
OV3 14
OV2 15
OV1 73
OSUB 11
VM1.3 7
VH 69
VHH 6
VL 17
GND 33
VDC 64
DVDD3 48
H2 47
DVSS3 75
DVDD3 46
H1 45
R 13
DVDD3 12
DVSS3 44
C4219
µ
0.1
R4210
0
R4203 C4207
#
OPEN
2-20(No.YF123)
L4202
L4203
µ
22
µ
22
T
C4217
C4216
10 µ /16v
4.7 µ /16v
TL4204
VDIN
HDIN
L4201
R4207
CLK1
µ
10
100
CDSTG_CS
C4222
4.7/16V
CAM_OUT
CAM_CLK
C4213
L4205
NQR0006-001X
0.1
R4208
0
V4
V3
V2
V1
C4202
L4204
0.1
µ
22
C4218
4.7 µ /16V
R4206
H2
0
R4205
H1
0 R4204
RG ADIN0
0
ADIN1
X4201
ADIN2
C4214
GND XOUT
ADIN3
7p
XIN GND
ADIN4
ADIN5
R4209
ADIN6
1M
ADIN7
ADIN8
ADIN9
yf123_y30334001a_rev1.1
REG_15V
TO REG
REG_-7.5V
REG_3.1V
GND
TL4203
TO MAIN IF
(CN104),
VDIN
PARAGON
HDIN
TO PARAGON
CLKI
CDSTG_CS TO CPU
CAM_OUT
TO CPU,
OP DRV
CAM_CLK
TO CPU
CDSTG_RST
ADIN0
ADIN1
ADIN2
ADIN3
ADIN4
TO PARAGON
ADIN5
ADIN6
ADIN7
ADIN8
ADIN9
Ref
R4202 R4203
Dest
Key
PAL 100K OPEN
NTSC OPEN 100K