Main(Mda) Schematic Diagram - JVC GR-D350UC Schematic Diagrams

MAIN(MDA) SCHEMATIC DIAGRAM

DRUM_PG
DRUM_FG
DRUM_REF
C_FRB
TO CPU
CAP_FG
CAP_REF
LD_ON
L_FRB
MDA_PS
C1601
0.01
LOAD_FWD
TO MAIN IF
(CN1601)
LOAD_REV
GND
D1602
OPEN
D_FG-
D_PG-
D_PFG+
TO MAIN IF
COIL_COM
(CN1602)
D_COIL_U
D_COIL_V
D_COIL_W
GND
0 1 MAIN(MDA)
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
TL1612
TL1618
TL1613
C1607
0.047
TL1619
TL1617
D.COM
D.U
D.V
R1614 0.33
D.RNF
D.W
NC
L.FRB
L.REF
L.FWD
NC
L.GND
L.REV
L.VM
C.FGIN+
C1614
µ
10 /10
C.FGIN-
C.FGAMP
R1612
68K
R1613
1K TL1608
C1621
TL1605
1
R1622
10K
C1629
0.22
R1620 R1621 R1629
68K 10K 560K
TL1606
C1605
0.1
TL1609
C1602
µ
10 /6.3
C1606
0.0015
T
R1603
4.7K
C1603
µ
10 /6.3
R1604
T
100K
R1601
680
R1602
120K
D.PGIN-
D.PGAMP
TL1610
D.PGSMT
TL1607
C.HW-
C1618 0.0022
C.HW+
C.HV-
C1619 0.0022
C.HV+
IC1601
C.HU-
C1620 0.0022
C.HU+
BD6637KV
NC
NC
C.W
C.RNF
C.V
C.U
NC
R1617
0.33
1 2 3
D1603
DAP222-X
R1635
6 4
Q1601
3.3K R1637
UMC3N-W 150K
R1636
12K
C1633
0.47
(No.YF123) 2-9 2-10(No.YF123)
TL1601
TL1602
C1632
OPEN
0.47 D1604
NMFZ007-R20X-K
F1601 R20
!
L1601 10
NQL382M-100X
T
C1631
TL1620
10/6.3
R1711 R1712
1K 1K
R1702
2.2K
R1710
120K
R1701
82K
R1703
2.2K
R1709
10K
8 7 6 5 8 7 6 5
IC1702 IC1701
LM393DR-X LM358DR-X
1 2 3 4 1 2 3 4
R1707
R1708 10K
120K R1706
82K
R1705 R1704
2.2K 2.2K
yf123_y20389001a_rev1.1
DRUM_ERR
TO REG
DRUM_PWR
GND
CAP_ERR
TO REG
CAP_PWR
M_UNREG
REG_3.1V
!
F1602 R50
NMFZ007-R50X-K
TO OP DRV,
M_REG4.8
REG
TO MAIN IF
(CN1603,1604)
MDA_2.9V
C_FG+
C_FG-
C_COIL_U
C_COIL_V
C_COIL_W
HG_W-
TO MAIN IF
(CN1603)
HG_W+
HG_V-
HG_V+
HG_U-
HG_U+
R1611
270
HG_BS+
HG_BS-
R1610
270
S_REEL
TO CPU
T_REEL
T_RL+
T_RL- TO MAIN IF
(CN1604)
S_RL+
S_RL-