Main(Cds/Tg) Schematic Diagram - JVC GZ-MG27US Schematic Diagrams

MAIN(CDS/TG) SCHEMATIC DIAGRAM

P_GYAMP
P_GYAMP 24
REG_3.1V 23
G_RST
G_RST 22
Y_GYAMP
Y_GYAMP 21
V4
V4 20
V3
V3 19
V2
V2 18
V1
V1 17
SUB
SUB 16
H2
H2 15
H1
H1 14
RG
RG 13
GND 12
GND 11
R4214
GND 10
100
CCD_OUT 9
GND 8
C4225
10p
GND 7
GND 6
CCD_CTL
CCD_CTL 5
CCD_-7.5V 4
CCD_-7.5V 3
CCD_15V 2
CCD_15V 1
CN105
QGF0547C2-24X
TO CCD(CN5001)
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
TP4203
[CCD_CTL]
L4205
56 53 52 35 32 30 29 25 24
10
T
C4224
47/6.3
55 VSS
C4221 0.1
82 VDD [CDS(ANALOG)]
57 DC_DET1
C4203 1
58 VDD [CDS(ANALOG)]
1
C4204
26 DC_DET2
C4210
0.1
84 CCD_OUT
C4205 1
59 DC_DET3
0.1
C4206
27 DC_DET4
85 AUX
60 VSS
1
C4208
28 VRB
C4209 1
61 VRT
86 DVDD1 [CDS(DIGITAL)]
62 DVSS1
74 NC
76 NC [TG/V DRV/CDS/AD]
77 NC
78 NC
83 NC
89 SUB
90 SUB
91 SUB
92 SUB
1 65 34 2 66 3 67 36 4 37 68 38 39 70 79 31 63 88 87 51 8 40 41
(No.YF133)2-17
L4203 22 µ
D4201
1SS355-X
L4202
µ
22
T
R4201
C4217
100k C4216
10/16
4.7/16
C4220
0.1
L4201
NQR0006-001X
50 16 14 15 73 11 49 7 17 5 69 6 33 64
EXDS2 80
EXDS1 21
TEST2 81
TEST1 54
NC 23
DVSS3 75
[H,RG] DVDD3 48
H2 47
[H,RG] DVDD3 46
H1 45
[H,RG] DVDD3 12
IC4201
R 13
NN12072A-X
DVSS3 44
X4201
NC 22
NC 20
XI 43
XO 72
PNSW 10
NC 19
NC 18
CCDSW 42
VCTRL 9
CLR 71
R4207
100
2-18(No.YF133)
0 1 MAIN(CDS/TG)
C4212
4.7/6.3
LAST NO VACANT NO
R 4227 4213 4216~4218
L 4205
L4204
C 4225 4222 4223
µ
22
IC 4202
C4218
D 4201
4.7/6.3
X 4201
TP4202
[SHD]
TP4201
[SHP]
CCD_CTL
R4206 10
H2
R4205
10
H1 FLSH_RST
TG2_RST
C4219
0.1
RG
R4204 10
NAX0804-001X
[36MHz X'TAL]
TG_CS
R4209
1M
CAM_OUT
XIN
GND
CAM_CLK
TG_VD
GND
XOUT C4214
TG_HD
7p
MCLKI
R4208 0Ω
TG2_RST ACHI9
FLSH_RST ACHI8
R4215 ACHI7
OPEN
ACHI6
C4207
OPEN
ACHI5
ACHI4
ACHI3
ACHI2
ACHI1
ACHI0
G_RST
P_GYAMP
Y_GYAMP
yf133_y30344001a_rev0.1
REG_3.1V
TO MAIN IF(CN103)
REG_-7.5V
REG+CCD TO MAIN IF,V I/O
CAM_3.1V TO MAIN IF(CN101,103)
GND
TO DSP
CCD_CTL
TO SUB CPU,DSP MEM
FLSH_RST
TO SUB CPU
TG2_RST
TO P.PRCS
TG_CS
CAM_OUT
TO P.PRCS,OP DRV
CAM_CLK
TG_VD
TG_HD
MCLKI
ACHI9
ACHI8
ACHI7
ACHI6
ACHI5
TO P.PRCS
ACHI4
ACHI3
ACHI2
ACHI1
ACHI0
G_RST
P_GYAMP
Y_GYAMP