Electronics Specifications - Toshiba B-SA4T Series Product Description

1. OUTLINE

1.5 Electronics Specifications

1) CPU: HD6417705F133BV
2) Memory
(1) Program:
(2) Backup:
(3) Image buffer + Work:
3) Interface
(1) Parallel interface (Standard interface)
Centronics interface conforming to IEEE1284, supporting SPP mode (compatibility mode) and
nibble mode.
Data input method:
Control signals
Compatibility mode
Nibble mode
Data input code: ASCII, JIS 8-bit code for European characters, 8-bit code for graphic
Receiving buffer: 1MB (shared with other interfaces)
Input/Output circuit configuration and Input/Output conditions
Type
Input/
Data 1 to 8
Output
nStrobe/HostClk
nInit/nReverseRequest
Input
nAutoFd/HostBusy/HostAck
nSelectIn/IEEE1284Active
Busy/PtrBusy/PeriphAck
nFault/nDataAvail/nPeriphRequest
Output nAck/PtrClk/PeriphClk
Select/XFlag
PError/AckDataReq/nAckReverse
16-MB Flash ROM
512-byte EE-PROM
16-MB SD-RAM
8-bit parallel (DATA 1 to 8)
nStrobe, nAck, Busy, PError, Select, nAutoFd, nInit, nFault, nSelectIn
HostClk, PtrClk, PtrBusy, AckDataReq, Xflag, HostBusy, nInit, nDataAvail,
IEEE1284Active
Signal Name
1- 7
Configuration
+5V
SN74LVX161284 or equivalent
1K
+5V
SN74LVX161284 or equivalent
1K
100P
SN74LVX161284
or equivalent
EO10-33016A
1.5 Electronics Specifications
Logical level
(input)
"1" = 2~5V
"0" = 0~0.4V
+5V
Logical level
(output)
1K
"1" = 2.4~5V
"0" = 0~0.4V
100P