Motorola A009 Service Manual page 58

DRAGONBALL CIRCUIT
VCC VCC VCC
U030-2
U032-2
P WR _ G N D P WR _ G N D
V C C V C C
G N D G N D
C a d e n c e a n d M e n t o r
s y m b o l s b u i l t d i f f e r e n t l y
D E V T B R D
J001
47 HEAD_INT_L (from Q008)
~DCABLE_INT
(from J003)
36
~CTS1
28
~RTS1
26
TP003 TP004
(UART1)
(to J600)
UTXD1
32
URXD1
30
XCVR_PWR
33
REG3V_MISC
BATT+
2
C 0 4 2
4
1 0 u F
6
8
10
12
14
16 R 2 0 8
1
2 . 2
3
5
7
9
11
13
17
WSIM2_PD
19 SIM2_CLK
20 SIM2_IO
15 SIM2_RST
49 HEAD_DET
34 AUX_MIC (from /to J003)
R 0 4 1
38 SPKR_OUT
0
18 V_BOOST1_REG
THERM
23
BATT_SER_DATA
21
SIM_CLK
29
SIM_RST
27
VSIM
25
SIM_IO
31
TP074
37
C 0 8 9 C 0 9 9
3 3 p F
3 3 p F
TP073
L 0 0 7
35
3 9 n H
50
B+
48
DBRX_WCTX
44
(UART2) DBTX_WCRX
46
DBRTS_WCCTS
(to U800)
40
DBCTS_WCRTS
42
GND
24
GND
22
~DW_INT
39
~WD_INT
41
GCAP_V2
43
WC_~RESET
45
VCC
VCC
IRDA_EN IRDA_EN
U031-2
P WR _ G N D
C 0 4 4
R 1 9 9 D N P V C C
R 0 0 4
3 3 p F
1 0 K 1 0 K
U031-1
D N P
G N D
U030-1
2 4
2
4
1
1
N C 7 S Z 1 2 5
N C 7 S Z 1 2 5
~IRDA_EN
TP005
1
4 2
U032-1
N C 7 S Z 1 2 5
VCC
TP022
C 0 4 5
3 3 p F
4,2 MHz
R 0 0 3 D N P
TFT_CLKI_PK0
R 2 0 7 D N P S H O R T
C 0 9 2
4 7
1 5 0 0 p F
R 2 1 6
1 K
U016
C 0 4 3
1 u F
IRDA
1 4
L E D A R X D
2
T X D
G 1
IRDA_EN 3 C A S E 1 DB~RESET
G 2
S D
C A S E 2
Y001
R 0 9 9 ~CSA0
1 0 0 K
~UWE
G P 2 W0 0 2 Y P
4 1
O U T 1 I N 1 ~LWE
3 2
N C O U T 2 I N 2 N C
TP050
9 5 L 0 8
BATT+ 32.768kHz
J002
C 0 0 2 C 0 0 1
2 0 p F 2 0 p F
1 3
P I N 1
P I N 3
2 4
P I N 2
P I N 4
BATTERY
CONN.
ADD (22:1)
J004
SIM CONN.
3 6
P I N 3 P I N 6
2 5
P I N 2 P I N 5 N C
1 4
P I N 1 P I N 4 VCC
C 0 4 6
0 . 1 u F
M C L S y m b o l d i f f e r e n t
MIC- f r o m C e l l u l a r S y m b o l
R 0 1 4
(from J008/ J003) 1 0 0 K
(from J008) REG3V_MISC_EN
MIC+
TP001 (to U028)
SPI_MISO
(from U029)
B+ SPI_CLK
(to U027)
(to U025)
U021-1 U022-1
TP002
4 2 4 2 TP056
TP057
U023-1
1
N C 7 S Z 1 2 5
~IPC_EN
4 2
N C 7 S Z 1 2 5 1
1
N C 7 S Z 1 2 5
VCC
U023-2
U021-2
P WR _ G N D P WR _ G N D P WR _ G N D
V C C V C C V C C
G N D G N D G N D
U022-2
VCC
R 0 9 7 R 0 0 5 R 0 0 6 R 0 0 7
1 0 K 1 0 0 K 1 0 0 K 3 3 0 K
TP006
~DTACK_PG0
~WP_OS
4 5 6 7
R_~W
DB_VDD
C 0 0 3 C 0 0 4
TP078
0 . 3 3 u F 1 0 0 p F
TP077
TP076
A 1 1
R E S E T
K 1
E X T A L
L 1
X T A L
J 1 2
C S A 0
B 9
U WE _ U B
C 9
L WE _ L B
E 9
T P 0
C 6
A0_TP
T P 1
J 6
T P 5
A 9
A 0 _ P G 1
1 B 8
A 1 _ M D 0
2 A 8
A 2 _ M D 1
3 B 7
A 3 _ M D 2 U001
4 A 7
A 4 _ M D 3
5 B 6
DRAGONBALL
A 5 _ M D 4
6 A 6
A 6 _ M D 5
7 C 5
A 7 _ M D 6
8 B 5
A 8 _ M D 7
9 A 5 S C 5 4 1 0 0 2 V F
A 9 _ M D 8
1 0 C 4
A 1 0 _ M D 9
1 1 B 4
A 1 1 _ M D 1 0
1 2 A 4
A 1 2 _ M D 1 1
1 3 B 3
A 1 3 _ M D 1 2
1 4 A 2
A 1 4
1 5 B 2
A 1 5
1 6 A 1
A 1 6
1 7 C 3
A 1 7
1 8 C 2
R 0 1 5 D N P
A 1 8
1 0 0 K 1 9 B 1
D N P
A 1 9
2 0 D 3
A 2 0 _ P F 3
2 1 D 2
A 2 1 _ P F 4
2 2 C 1
A 2 2 _ P F 5
D 1
A 2 3 _ P F 6
J 5
SPI_MOSI
P J 0 _ M O S I
H 4
P J 1 _ M I S O
G 4
P J 2 _ S P I C L K
G 3
SPI_SS P J 3 _ S S *
E 3
P J 4 _ R X D 2
E 4
P J 5 _ T X D 2
F 3
P J 6 _ R T S 2
F 4
P J 7 _ C T S 2
TP058
TP059
R 1 5 0
(from U012 / Reset Circuit)
1 0 K
SIGNALS ARE ONLY
IN USE WITH LCD
DISPLAY
DB_VDD
VCC
Groud to enter
R 0 0 8
Bootstrap mode
1 0 0 K
C 0 0 5
1 u F
R 0 1 6
TP007
4 . 7 K
U002
~POT_CS
SER_NUM_BUS
2 3 NC
D A T A N C 1
TP053 4 NC
F O R E M I N C 2
TP023
~ABORT R 0 0 2 D N P
S H O R T D S 2 4 0 1 P
D N P
5
NC
DB_CLKO
N C 3
6 NC
~CSA1 N C 4
KEYDRIVE(7:0)
0 1 2 3
TP075
R 0 0 9 D N P
3 3 0 K
D N P
B 1 0
~OE
E N _ O E
WC_~RESET
L 6
P D 0 _ I N T 0
M 5
P D 1 _ I N T 1 *
K 5 ~WD_INT
P D 2 _ I N T 2
L 5
PHOTO_DET
P D 3 _ I N T 3
M 4
~EXT_DUART_IRQ
P D 4 _ I R Q 1 *
L 4
P D 5 _ I R Q 2 * ~KBD_INT
M 3
P D 6 _ I R Q 3 *
L 3
~PFAIL
P D 7 _ I R Q 6 *
J 1 0
P C 0 _ L D 0
LCD_D0
M 9
P C 1 _ L D 1 LCD_D1
L 9
P C 2 _ L D 2 LCD_D2
K 9
LCD_D3
P C 3 _ L D 3
L 8
P C 4 _ L F R M LCD_FRM
K 8
P C 5 _ L L P
LCD_LP
M 7
P C 6 _ L C L K LCD_CLK
L 7
LCD_ACD
P C 7 _ L A C D
K 1 2
P B 0 _ C S B 0 * ~VLCD_EN
L 1 2
P B 1 _ C S B 1 * ~CSB1_PB1
K 1 1
P B 2 _ C S C 0 * _ R A S 0 *
~CSC0
L 1 1
P B 3 _ C S C 1 * _ R A S 1 * BKLT_EN
M 1 2
P B 4 _ C S D 0 * _ C A S 0 *
M 1 1
P B 5 _ C S D 1 * _ C A S 1 *
M 1 0
ALERT_FREQ
P B 6 _ T O U T * _ T I N
L 1 0 ALERT_SPL
P B 7 _ P WM O
0
B 1 2
P A 0 _ D 0
1
B 1 1
P A 1 _ D 1
2
C 1 2
P A 2 _ D 2 3
C 1 1
P A 3 _ D 3 4 TP020
DATA(15:0)
C 1 0
P A 4 _ D 4 5
D 1 2
P A 5 _ D 5 6
D 1 1
P A 6 _ D 6
7
E 1 2
P A 7 _ D 7
8
E 1 1
D 8 9
E 1 0
D 9
1 0
F 1 2
D 1 0 1 1
F 1 1
D 1 1 1 2
G 1 2
D 1 2
1 3
G 1 1
D 1 3 1 4
H 1 0
D 1 4
1 5
H 1 1
D 1 5
POT_U_~D
~POT_INC
(from Q006)
VCC
REG3V_MISC
U017
R 0 0 1 D N P
0
B O A R D S H O R T
2
G N D
D N P
M M 1 4 2 6 X N L E
1
C O N T
C 0 0 6 C 0 0 7 C 0 0 8
0 . 1 u F 0 . 1 u F 0 . 1 u F 3
N C N C
R 1 9 2
1 0 K
CR07
C 0 4 8
7 C 0 4 7
TP021
3 3 p F
4 . 7 u F
VM01
3
VCC
T A B
VCC
R 0 6 1
2 . 7
R 0 6 2
R 0 1 0 R 0 1 1 R 0 1 2 U018
1 0 0 K
3 3 0 K 3 3 0 K 3 3 0 K C 0 4 9
LIDSWITCH
0 . 1 u F
TP016
1 2
S U P P L Y O U T P U T
TP012
A 3 2 1 0 E L H
TP014
~LID_CLOSED
C 0 3 5 C 0 5 0
Q007
1 0 0 p F 1 0 p F
U014
L M C 7 2 1 1
4 2
1
R 0 4 6
3
5
1 0 K
TP015
R 0 4 9 R 0 4 7
TP013
4 . 7 M E G 1 K
R 0 4 8
(from Q006)
REGV_MISC
1 0 0 K
TP017
LCD_EN
R 0 5 4
~KBD_CS
Q011
1 0 0
(from Q006) TP018
REGV_MISC
R 0 5 5
Q013 LS01
1 0 0
Q012
2
6
P O S 1
1 1
N E G 1
3
N E G 2
TP019
4
2
N E G 3
3
4
R 0 5 9
3 0
R 0 5 8
5 1
GREEN
DS01
RED
R 0 1 3 D N P
L N J 1 1 5 W8 P 0 M T
1 0 0 K
D N P
~PHONE_MODE
(to Q004/Q005)
WC_~RESET
(to U012)