Motorola A009 Service Manual page 52

B C
A
V2
1
DB_ ~ RTS
(from P900)
Q600
TESTPOINTS
TP838 R_W
TP824 CE0 (FLASH_CS)
TP822 CE1 (FLASH_OE)
TP825 CE2 (RAM_LB) MUX_UTXD
TP826 CE3 (RAM_UB)
TP828 VCLK
RS232_TX (WAS SCI_TX)
TP831 VDR
RS232_RX (WAS SCI_RX)
2
TP830 VDX
TP829 VFSRX
TP834
MQSPI_CLK2
TP835 DR2
TP836
DX2
SIMPD0
TP832 MQSPI_CS0
DIG_AUD (3:0)
BOOM_EN
U907
B+
3 DB_~CTS
(from P900)
VREF
BATT_FDBK
Q911
KBR3
CR600
4
MAN_TEST_AD
EXT_B+
J600
CR601
V2
(UART1)
SW_RF
DB_~CTS / BATT_FDBK
MAN_TEST
MAN_TEST_AD
RS323_TX (DB_UTXD)
RS232_RX (DB_URXD)
V1
~
RS232_EN (DB_ RTS)
ON/OFF
5
UPLINK
DOWNLINK
DSC_EN
STBY_DL V2
V1_SW
DCABLE_INT
Q912
V2
Q913
Q810
6
V1
DOWNLINK_AD
V_BOOST1_REG
V2 STBY_DL
(from P900)
BATT+
THERM
Q914 BATT_THERM_AD
BATT_SER_DATA
7
CR603
DR2
DX2
MQSPI_CLK2
MQSPI_CS0
V2 V2
V2
BATT+
U905
8
Q908
BATT_FDBK
V1
V2 V2
CR500
CR500
UPLINK
9 V2
Q505
LED_GRN
Q505
LED_RED
VCLK
VDR
VDX
VFSRX
VAG
10
V2
(from P900)
MIC+
(from P900)
HEAD_DET
(to U800)
J504
HEAD_INT_L (from P900)
AUX_MIC
CR970
11
CR950
CR501
ON_2
A009 - AL SCHEMATICS
D E F
(to U900)
SIM_TX
DB_UTXD
(from P900)
DB_URXD
SIMPD0
CLK_SELECT
(to P900) (from P900)
STBY_DL
~ ~
WC_ RTS1 WC_ CTS1
U906
CR912
TIMING8
TIMING7
TIMING6
TX_EN
TX_KEY
DM_CS
RX_EN
RX_ACQ
DSC_TXD DSC_RXD
RFI
RCLOCK
KBR4
V2
KBR3
KBR2
KBR1
KBR0
VDDS
V1_SW
KBC4
INTR_OUT2
KBC3
V2
KBC2
KBC1
KBC0
Q800
Q800
INTR_OUT1
CHRG_EN
V_BOOST1
LED_RED
V2 LED_GREEN
VRVA_INT
SIM2_PD
SIM2_RST
SIM2_CLK
SIM2_IO
V2
RTC_BATT+
B+
WDOG
B+_FREAK
Y900
32,768kHz
V_BOOST1
V_BOOST1 CR902
PWR_SW
U900
B+
B+
BATT+
VREF
SIM_RX
SIM_TX
MIC_BIAS
STBY_DL B+
V2
VAG
U901
SPKR+
G H I J
TDO
TMS
TRST* VCC_MEMIF VCCA
TCK
EMU1
V2
TDI
EMU0
RESET
CE4 CE5
U800
WHITECAP
VCCA
VDD
MIDRATE_1
MIDRATE_2
VDDS
VCC_MEMIF
MAGIC_QSPI(3:0)
GCAP_MQSPI(3:0)
V3
VDD
DR1
DX1
MQSPI_CLK1
MQSPI_CS1
VCCA
V2
EXT_B+
Q905 B+
CR903
BATT+
MIDRATE_1 Q904
Q901
CHRG_EN
Q903
EXT_B+
Q900
EXT_B+
MIDRATE_2
Q909 Q909
AUX_MIC KBR0
MIC_BIAS
U908
VSIM1 HEAD_DET
SIM_IO
SIM_CLK
SIM_RST
RX SIGNAL PATH
TX SIGNAL PATH
RTC_BATT+
SPKR-
MAIN VCO SIGNAL PATH
J905
TUNING VOLTAGES
13 MHz REFERENCE CLOCK
DATA BUS
ADDRESS BUS
TEXT REFERENCE SIGNALS
K L
M
-5V V1 -10V
VDDS VDD
U903 U904
A20
ADDRESS(21:0)
A0
V2
V2
SR_VCC
U703
U701
U702
V2
V2
SR_CS
CE8
MAGIC_13MHz
DATA(15:0) DATA(15:0)
ON_2
CR905
PWR_SW
(from /to P900)
~ ~
DW_INT WD_INT
Q907
KBC3
XCVR_PWR
(from P900)
KBR1
KBR0
KBC2
KBC1
KBC0_FREAK
V2
KBC0
KBR3
CR904
VR905
VR903 VR904
CONTL. SIGNAL
TRANC. SIGNAL P900 P900
19
GND 1 GND
27
2
BATT+ BATT+
28
3
GND GND
31
BATT_FDBK BATT+ 4 BATT+
Q902
GND 5 GND 33
6
BATT+ BATT+ 35
GND 7
GND 36
BATT+ 8 BATT+
37
GND 9 GND
38
10
BATT+ BATT+
GND 11 39
GND
BATT+ 12 BATT+
40
GND 13 GND
50
14
BATT+ BATT+
15
SIM2_RST SIM2_RST
BATT+ 16 BATT+
SIM2_PD 17 SIM2_PD
18
V_BOOST1_REG V_BOOST1_REG
SIM2_CLK 19 SIM2_CLK
SIM2_IO 20 SIM2_IO
BATT_SER_DATA 21 BATT_SER_DATA
22
GND GND
THERM 23 THERM
GND 24 GND
VSIM1 25 VSIM
KBR3
26
DB_ ~ RTS ~ RTS1
27
SIM_RST SIM_RST
Q2121
(UART1) ~ 28 ~ CTS1
DB_ CTS
29
SIM_CLK SIM_CLK
RS232 EXT.
30
to/from Q600, DB_URXD URXD1
J600 and U907 SIM_IO 31 SIM_IO
Q2122
DB_UTXD 32 UTXD1
33
(to Q907) XCVR_PWR XCVR_PWR
AUX_MIC 34
AUX_MIC
35
MIC+ MIC+
DCABLE_INT 36 ~ DCABLE_INT
37
MIC- MIC-
38
SPKR- SPKR_OUT (NC)
~ DW_INT 39 ~
DW_INT
WC_ ~ CTS1 40 DBRTS_WCCTS
~ 41
WD_INT ~ WD_INT
(UART2)
~ 42
WC_ RTS1 DBCTS_WCRTS
Interprocessor
43
V2 GCAP_V2
Comunication
WC_UTXD1 44 DBRX_WCTX
between U800
45
and U001 RESET WC_ ~ RESET
46
WC_URXD1 DBTX_WCRX
HEAD_INT_L 47 HEAD_INT_L
B+ 48 B+
49
HEAD_DET HEAD_DET
B+ 50 B+
N
SMART
S523
VOL_UP
S508
VOL_DOWN
S512
VR906
SIM2_CLK
SIM_RST
DB_ CTS
SIM_IO
XCVR_PWR
MIC+
DCABLE_INT
SPKR-
~
DW_INT
WC_ CTS1
B+