Integra DTR-4.5 Service Manual page 57

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS
MX29LV040 (4M-Bit CMOS Single Voltage 3V Only Equal Sector Flash Memory)
BLOCK DIAGRAM
CE
OE
WE
A0-A18
TE
L 13942296513
PIN LAYOUT
A11
1
A9
2
A8
3
A13
4
A14
5
A17
6
WE
7
www
VCC
8
A18
9
A16
10
A15
11
A12
12
.
A7
13
A6
14
A5
15
A4
16
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CONTROL
INPUT
LOGIC
ADDRESS
LATCH
AND
BUFFER
Q0-Q7
32
31
30
29
28
27
26
25
MX29LV040
24
x
ao
u163
23
y
22
21
i
20
19
18
17
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2 9
8
PROGRAM/ERASE
HIGH VOLTAGE
MX29LV040
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
Q Q
PGM
3
6 7
1 3
1 5
SENSE
DATA
AMPLIFIER
HV
PROGRAM
DATA LATCH
I/O BUFFER
TERMINAL DESCRIPTION
Pin Name
A0~A18
OE
A10
Q0~Q7
CE
Q7
CE
Q6
Q5
WE
Q4
Q3
OE
GND
co
Q2
GND
Q1
Q0
VCC
.
A0
A1
A2
A3
9 4
2 8
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
COMMAND
DATA
DECODER
0 5
8
2 9
9 4
2 8
COMMAND
DATA LATCH
Description
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
m
Output Enable Input
Ground Pin
+3.0V single power supply
DTR-4.5
9 9
9 9

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