Integra DTR-4.5 Service Manual page 47

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3 7 63 1515 0
IC BLOCK DIAGRAMS AND DESCRIPTIONS
ADV7183AKST(Multiformat SDTV Video Decoder)
TE
L 13942296513
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12
CLAMP
AIN1–AIN12
INPUT
CLAMP
MUX
CVBS
S-VIDEO
YPrPb
CLAMP
SYNC PROCESSING AND
CLOCK GENERATION
SCLK
SERIAL INTERFACE
SDA
CONTROL AND VBI DATA
ALSB
80
79
78
77
VS
1
HS
2
DGND
3
DVDDIO
4
P11
5
P10
6
P9
7
P8
8
DGND
9
DVDD
10
NC
11
SFL
12
NC
13
DGND
14
DVDDIO
15
NC
16
NC
17
NC
18
P7
19
P6
20
21
22
23
24
NC = NO CONNECT
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i
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8
10
DATA
A/D
PREPROCESSOR
10
10
A/D
10
DECIMATION AND
DOWNSAMPLING
10
FILTERS
A/D
SYNC AND
CLK CONTROL
CONTROL
AND DATA
Q Q
3
6 7
1 3
76
75
74
73
72
71
70
69
ADV7183A
TOP VIEW
(Not to Scale)
25
26
27
28
29
30
31
32
u163
80-lead LQFP pin configulation
.
2 9
9 4
2 8
1 5
0 5
8
2 9
9 4
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
33
34
35
36
37
38
39
40
m
co
DTR-4.5
9 9
2 8
9 9
AIN5
AIN11
AIN4
AIN10
AGND
CAP C2
CAP C1
AGND
CML
REFOUT
AVDD
CAP Y2
CAP Y1
AGND
AIN3
AIN9
AIN2
AIN8
AIN1
AIN7

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