Integra DTR-4.5 Service Manual page 50

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3 7 6 3 1 5 1 5 0
Compressed
Digital
Interface
T E
L 1 3 9 4 2 2 9 6 5 1 3
Digital
Audio
Input
DSP AB
PLL Clock
Manager
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Frame
Multi-Standard
Shifter
Audio Decoder
Input
Paraller or Serial
Buffer
Host Interface
RAM
x
a o
u 1 6 3
y
i
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8
9
SAI0
Serial
SAI1
Audio
SAI2
Interface
SAI3
DSP C
Programmable
Q Q
32-Bit DSP
3
7
6
3
1
5
1
DSP
DSP
ROM
RAM
c o
.
2
4
2
9
8
External Memory
Interface
Digital
DAO 0
Audio
Output
DA01
5
0
8
9
2
4
9
8
2
GPIO and I/O
Controller
Paraller or Serial
Host Interface
m
9
9
9
9

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