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3 7 63 1515 0
IC BLOCK DIAGRAMS AND DESCRIPTIONS
ADV7183AKST(Multiformat SDTV Video Decoder)
Pi n Function Descri ptions
Pin No.
Mnemonic
3, 9, 14, 31, 71
DGND
39, 40, 47, 53, 56
AGND
4, 15
DVDDIO
10, 30, 72
DVDD
50
AVDD
38
PVDD
41...46, 57...62
AIN1...AIN12
11, 13, 16...18, 25,
NC
34, 35, 63, 65, 69,
70, 77, 78
5...8, 19...24,
P0...P15
32, 33, 73...76
2
HS
1
VS
80
FIELD
67
SDA
68
SCLK
66
ALSB
64
RESET
27
LLC1
TE
26
LLC2
L 13942296513
29
XTAL
28
XTAL1
36
PWRDN
79
OE
37
ELPF
12
SFL
51
REFOUT
52
CML
48, 49
CAPY1,
CAPY2
54, 55
CAPC1,
CAPC2
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Type
Function
G
Digital Ground.
G
Analog Ground.
P
Digital I/O Supply Voltage (3.3 V )
P
Digital Core Supply Voltage (1.8 V).
P
Analog Supply Voltage (3.3 V).
P
PLL Supply Volt age (1.8 V).
I
Analog Video Input Channels.
No Connect Pins.
O
Video Pixel Output Port.
O
HS is a horizontal synchronization output signal.
O
VS is a vertical synchronization output signal.
O
FIELD is a field synchronization output signal.
2
I/O
I
C Port Serial Data Input/Output Pin.
2
I
I
C Port Serial Clock Input (Max Clock Rate of 400 kHz).
I
This pin selects the I
for a write as 0x40; fo r ALSB set to logic high, the ad d ress se lected is 0x42.
I
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7183A circuitry.
O
This is a line- locked output clock for the pixel data output by the ADV7183A. Nominally
27 MHz, but vari es up or down a ccording to video line length.
O
This is a divide-by-2 version of t he LLC1 output clock for the pixel data output by the
ADV7183A. Nominally 13.5 MH z, but varies up or down according to video line length.
I
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3 . .3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
O
This pin should be connected to the 27 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183A. In crystal mode,
the crystal must be a fundamental crystal.
I
A logic low on this pin places the ADV7183A in a power-down mode. Refer to the I2C
Control Register Map for more options on power-down modes fo r the ADV7183 A.
I
When set to a lo g ic low, OE enable s the pixel output bus, P15...P0 of the ADV7183A. A logic
high on the OE pin places Pins P15 ...P0, HS, VS, SF L /SYNC_OUT into a high impedance state.
I
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 42.
O
Subcarrier Frequency Lock. This pin contain
the subcarrier fr equency when this decoder is connected to any Analog Devices, Inc. digital
video encoder.
O
Internal Voltage Reference Output. Refer to Figure 42 for a recommended capa citor
network for this pin.
O
The CML pin is a common-mode level for the internal ADCs. Refe r to Figure 42 for a
recommended capacitor network for this pin.
I
ADC s Capacitor Network. Refer to Figure 42 for a recommende d capacitor network for
this pin.
I
ADC s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for
this pin.
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2 9
8
.
2
C address for the ADV7183A. ALSB set to Logic 0 sets the address
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
0 5
8
2 9
9 4
2 8
a se rial output stream that can be used to lock
s
m
DTR-4.5
9 9
9 9
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