Pll Circuits - Icom IC-7400 Service Manual

4-2-9 TEMPERATURE PROTECTION CIRCUIT
(MAIN AND RF UNITS)
The cooling fan (CHASSIS; MF1) is activated while transmit-
ting or when the temperature of the power amplifier exceeds
the preset value. The temperature protection circuit consists
of Q801, Q802 and D802 (MAIN unit), IC1101 and
Q2003–Q2005 (RF unit), and VARISTOR-A/B/C/D boards.
While transmitting, IC1101 (RF unit) outputs FANL signal to
Q2003 (RF unit). Then Q2003 (RF unit) is turned ON, Q801,
Q802 (MAIN unit) provide a voltage to the cooling fan to ro-
tate at low speed. The VARISTOR-B board, detects the tem-
perature of Q6; PA unit (VARISTOR-D board for Q202; PA
unit), and IC1101 (RF unit) outputs FANM signal and acti-
vates Q2004 (RF unit) to accelerate the cooling fan at
medium speed when the detected temperature exceeds
70˚C (158˚F). When the detected temperature is at 80˚C
(176˚F) or more, IC1101 (RF unit) outputs FANH signal and
activates Q20065 (RF unit), the cooling fan rotates at high
speed.
The temperature protection circuit keeps the cooling fan ro-
tating even while receiving until the Q6 (PA unit) or Q202's
(PA unit) temperature drops to 60˚C (140˚F) or below.
4-2-10 MONITOR CIRCUIT
(DSP UNIT AND MAIN UNIT)
The microphone audio signals can be monitored to check
voice characteristics.
(1) When FM/AM modes (MAIN UNIT)
A portion of the microphone audio signals are passed
through the DSP unit, and then applied to the AF amplifier
circuit as the MONI signal.
(2) When SSB/RTTY modes (DSP UNIT)
A portion of the transmit IF signal from the DSP IC (IC301)
is mixed with a 36 kHz LO signal to demodulate into the AF
signals. The demodulated signals are level-shifted 3.3 V to
5 V at the level converter (IC101) and then applied to the
D/A converter (IC102) to convert into the analog AF signal.
The AF signals are then applied to the MAIN unit as the
MONI signal.
The MONI signal from the DSP unit is amplified at the AF
amplifier (MAIN unit; IC1060, pins 5, 7) and passed through
the analog switch (MAIN unit; IC1040) and then applied to
IC1180 (MAIN unit). The applied signal is amplified at the AF
amplifier section (pins 2, 4) and volume controlled at the
VCA section (pins 7, 9). The volume controlled AF signals is
applied to the AF amplifier circuit (MAIN unit; IC1240).

4-3 PLL CIRCUITS

4-3-1 GENERAL
The PLL circuits generate a reference frequency (32.000
MHz); 1st LO frequencies (64.485–238.455 MHz); 2nd LO
frequency (64 MHz), 3rd LO frequency (419.000 kHz).
The 1st LO PLL adopts a mixer-less dual loop PLL system
and has 4 VCO circuits which cover from 30 kHz to 174 MHz.
The 1st LO and 3rd LO use DDSs, while the 2nd LO uses
the fixed frequency of the crystal oscillator.
4-3-2 1ST LO PLL CIRCUIT (RF UNIT)
The 1st LO PLL contains a main and reference loop as a
dual loop system.
The reference loop generates an approximate 10.8 MHz fre-
quency using a DDS circuit, and the main loop generates a
64.485 to 238.455 MHz frequency using the reference loop
frequency.
(1) REFERENCE LOOP PLL
The oscillated signal at the reference VCO (Q1301, D1301)
is amplified at the amplifiers (Q1302, Q1102) and is then ap-
plied to the DDS IC (IC1101, pin 46). The signal is then di-
vided and detected on phase with the DDS generated
frequency.
The detected signal output from the DDS IC (pin 56) is con-
verted into DC voltage (lock voltage) at the loop filter (R1135,
R1138, C1121) and then fed back to the reference VCO cir-
cuit (Q1301, D1301).
(2) MAIN LOOP PLL
The oscillated signal at one of the main loop VCOs (VCO
board, Q1201, D1201, Q1221, D1221, Q1241, D1241,
Q1261, D1261) is amplified at the buffer amplifiers (PLL
board, IC1802, Q1281) and is then applied to the PLL IC
(IC1801, pin 4). The signal is then divided and detected on
phase with the reference loop output frequency.
The detected signal output from the PLL IC (pin 13) is con-
verted into a DC voltage (lock voltage) at the loop filter and
then fed back to one of the VCO circuits (VCO board, Q1201,
D1201, Q1221, D1221, Q1241, D1241, Q1261, D1261).
The oscillated signal from the buffer amplifier (IC1802) is also
applied to the MAIN unit as a 1st LO signal after being dou-
bled or passed through the low-pass filter.
• Using VCO and 1st LO frequencies
Operating
Using VCO
frequency
0.03–
Q1201, D1201
7.999999 MHz
8.0–
Q1221, D1221
21.999999 MHz
22.0–
Q1241, D1241
39.999999 MHz
40.0–
Q1261, D1261 104.4550–124.455000 MHz
60.000000 MHz
108.0–
Q1241, D1241
143.999999 MHz
144.0–
Q1261, D1261
174.000000 MHz
4-3-3 2ND LO AND REFERENCE OSCILLATOR
CIRCUITS (RF UNIT)
The reference oscillator (X1901, Q1901) generates a 32.0
MHz frequency for the 2 DDS circuits as a system clock and
for the LO output. The oscillated signal is doubled at the dou-
bler circuit (Q1903, Q1904) and the 64.0 MHz frequency is
picked up at the double tuned filter (L1903, L1904). The 64.0
MHz signal is applied to the RF circuit as a 2nd LO signal.
4 - 6
1st LO frequency
64.4850–72.454999 MHz
72.4550–86.454999 MHz
86.4550–104.454999 MHz
172.4550–208.454999 MHz
(with doubler)
208.4550–238.455000 MHz
(with doubler)