Raytheon Pathfinder 1200 Instruction Manual page 84

buffer memory will be 112 bits for the video data of each transmission. Three trans-
missions of video data are stored in the buffer memory (IC7) for the interference
rejection circuit. The video data is written into the memory by the writing pulse fed
to IC7-14. The address data is fed on AO-A8 and the read data appears on
DO (lC7-7).
5) Interference Rejecter
The video data sent to the video RAM from the interference rejecter circuit is
delayed by two transmissions. The video data of the last-three transmissions is stored
in the, buffer memory IC7. This video data is read serially in each range step by A7
i
and A8 address control. No. I and No.2 data of IC7-7 are latched on IC8 by timing
control. After latching, No.3 data is present at IC7-7. These three data are fed to
NOR gate IC9-6 and added. No. I and No.2 data are fed to NAND gate ICII-12,
No.2 and No.3 data are fed to NAND gate ICII-6. The interference noise pulse
which is not synchronized to the transmission timing cannot pass through IC11-12
or IC 11-6. The output pulses of IC11-12 and IC11-6 are fed to NOR gate IC12-6
and added. ICIO-6 output appears in the IR switch "OFF" state. IC12-6 output
appears in the IR switch "ON" state. IC9-12, IC12-11, IC I0-11, IC11-8, IC12-8,
IC9-8, and IC13 are used for making the required latch pulses and the address control
data for the buffer memory.
6) Video RAM
The output of the interference rejecter circuit is added with the marker pulse
by NOR gate IC20-8 and fed to "AND" gate IC61-12. IC61-12 is the "AND"
gate for writing zero to video RAM in the "STANDBY" position of the POWER
switch.
The video RAM consists of four 16K (16,384) bits dynamic random access
memory ICs in a parallel connection.
Video data, multiplex address data, row address strobe pulse, column address
strobe pulse, and writing pulses are fed to IC65-IC68.
7) Gate Generator
The gate generator IC22 is triggered by the delay circuit IC34-8 output, and the
output of IC22-9 goes to "High" state. Clear pulse from IC20-12 of the buffer
memory address counter circuit is fed to IC22-13 (CR2) after 112 video data sampling
samples and the output of IC22-9 returns to "0" state. The output duration of
IC22-9 is varied at each range as follows:
RANGE (nm)
0.25 0.5 2 4 8 12
Time (usee)
6.4 6.4 12.8 25.6 51.2 102.4 153,.6
The outputs of IC22-9 (Q2) is fed to the sampling clock oscillator and the other
circuits. IC22-5 produces the address data selector control pulse of the interference
rejecter circuit.
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