Raytheon Pathfinder 1200 Instruction Manual page 70

15) Bearing Pulse Generator
The bearing pulse generator synchronizes the signal of the motor encoder into
the display timing. The output of this circuit is fed to the bearing counter circuit and
the main trigger generator circuit.
16) Main Trigger Generator
The main trigger generator circuit produces the trigger pulse for the transmitter
and display control timing.
,~.
17) Transmitter Trigger Generator
The transmitter trigger generator produces the pulse for driving the modulator
in the scanner unit.
18) Delay Circuit (0 nm Adjust)
The delay circuit produces a variable delay time for adjusting the PPI center to
o
nm as compensation for transmitter firing delays.
19) Gain-STC (Sea Clutter) Circuit
The Gain-STC circuit controls the sensitivity of the receiver in response to the
setting of the Gain and Sea Clutter controls on the control panel. At sea, the effect
of random signals received from waves at short ranges can be reduced with the sea
clutter control.
20) Clear Pulse Generator
The clear pulse generator produces the pulse for resetting the bearing counter
to zero. The Clear Generator is triggered by the SHM Pulse.
21) Bearing Counter
The bearing counter produces the antenna position data from the motor-encoder
output and the SHM signal in the scanner unit.
22) RO/XY Converter
The RO/XY converter circuit produces the pulse train for changing the bearing
data and the range data into the X and Y address data.
23) X Address Counter
The X address counter produces the X address data for writing the Video RAM.
24) Y Address Counter
The Y address counter produces the Y address data for writing the Video RAM.
25) Marker Generator
The marker generator produces two marker pulses at 0.25 and 0.5 nm ranges
and four marker pulses at 1, 2, 4, 8 and 12 nm ranges for input to the Video RAM.
26) Address Data Select
The address data select circuit inputs 7 bits X/Y counter address data or H/V
control data to the Video RAM address (depending on timing of read/write), ROM
address, latch and/or column address latch to the Video RAM address.
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