Display Unit - Raytheon Pathfinder 1200 Instruction Manual

6.3 DISPLAY UNIT
6.3.1 General
Most of the display unit components are mounted on five printed circuit boards; the
remaining components are chassis mounted. The display unit circuitry consists of the
main control, control panel, power supply, CRT display, and CRT display video circuits.
6.3.2 Main Control Circuits
1) Video Circuit
The incoming negative going video signal is fed to the FTC (Rain-Clutter) circuit.
The FTC circuit consists of a capacitor CIa, a resistor R22, and a diode
CD~.
CD3
operates as a diode switch which is controlled by the RAIN CLUTTER switch on the
display unit control panel via the Transistor TR3. In the "OFF" state of the RAIN
CLUTTER switch, CD3 is conductive, and the video signal is fed to the inverting
amplifier without being differentiated. In the "ON" state of the RAIN CLUTTER
switch, CD3 is not conductive, and the video signal is differentiated by cia and R22.
The negative going output of the FTC circuit is amplified by TR4 and the
inverted (positive going) output signal appears on the TR4 collector. The output of
the inverting amplifier is fed to the de restorer circuit via the emitter follower TR5.
The de restorer circuit consists of CD5 and followed by TR6. TR6 is an emitter
follower and drives the tuning indicator circuit and the comparator. The positive
going output signal of TR6 is fed to the integrator circuit C 16 and changed into dc
voltage. The de voltage across C 16 biases TR8 Base and controls the brilliance of the
Tuning Indicator LED. TR 7 controls the maximum brilliance of the Tuning Indicator
LED which is determined by the BRIL switch setting on the front control panel.
2)
Comparator
The comparator IC2 changes the analog video signal into a digital pulse train and
produces the negative going pulses on IC2-7. The output of IC2 is inverted by IC 14.
3) Pulse Stretch
The positive going digital video pulses are fed to the pulse stretch circuit. The
pulse stretch circuit consists of eight bits shift register IC3 and NOR gates, IC4 and
lC5. IC3 produces eight delayed pulses, and the delay time between pulses is controlled
by the clock pulses on IC3-8.
The clock pulse frequency is selected by the transmitter pulse width signal deter-
mined by setting the RANGE switches. The clock pulse frequency is 17.5 MHz at
short pulse and 4.375 MHz at long pulse. Two outputs Ql
+
Q2, or five outputs
(Ql - Q5) or all of eight outputs (Ql - Q8) are fed to the NOR gates and added to
the input pulse. The stretched output pulses appear on IC5-6, IC5-12 and IC5-8
and selected by IC6. IC6 is a data selector IC and controlled by RANGE data signal
(Ra, R 1, R2).
4) Buffer Memory
The output video pulses of the pulse stretch circuit are fed to the buffer memory
(lC7). The displayed range is divided into 112 range cells. Therefore, the required
6-15