Yamaha LSI YMF744B Technical Manual page 56

YMF744B
4-5. AC-link (Fig.6)
Item
CBCLK Cycle Time
CBCLK High Time
CBCLK Low Time
CSYNC Cycle Time
CSYNC High Time
CSYNC Low Time
CBCLK to Signal Valid Delay
Output Hold Time for CBCLK
Input Setup Time to CBCLK
Input Hold Time for CBCLK
Warm Reset Width
Note) Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, C
*13: This characteristic is applicable to CSYNC and CSDO signal.
*14: This characteristic is applicable to CSDI signal.
CBCLK
t
CVAL
SYNC
t
CVAL
CSDO
CSDI
Symbol
t
CBICYC
t
CBIHIGH
t
CBILOW
t
CSYCYC
t
CSYHIGH
t
CSYLOW
t
CVAL
t
COH
t
CISU
t
CIH
t
CBICYC
2.0 V
t
CBIHIGH
t
CBILOW
t t
CISU CIH
Fig.6: AC-link timing
Condition Min.
35
35
*13
*13 0
*14 15
*14 5
1.5 V
t
t
CSYHIGH
t
COH
2.0 V
0.8 V
2.0 V
0.8 V
-56-
Typ. Max.
- 81.4 -
40.7 45
40.7 45
- 20.8 -
- 1.3 -
- 19.5 -
- - 20
- -
- -
- -
- 1.3 -
=50 pF
L
0.8 V
t
COH CSYLOW
2.0 V
t
CSYCYC
February 3, 1999
Unit
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
1.5 V
0.8 V