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YMF744B
4-3. PCI Interface
Item
PCICLK Cycle Time
PCICLK High Time
PCICLK Low Time
PCICLK Slew Rate
PCICLK to Signal Valid Delay
Float to Active Delay
Active to Float Delay
Input Setup Time to PCICLK
Input Hold Time for PCICLK
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, C
*11: This characteristic is applicable to REQ# and PCREQ# signal.
*12: This characteristic is applicable to GNT# and PCGNT# signal.
PCICLK
OUTPUT
Tri-State
OUTPUT
(Fig.3, 4)
Symbol
t
PCYC
t
PHIGH
t
PLOW
-
t
(Bused signal)
PVAL
t
(Point to Point)
PVAL(PTP)
t
PON
t
POFF
t
(Bused signal)
PSU
*11 (Point to Point)
t
PSU(PTP)
*12 (Point to Point)
t
PH
PCICLK
t
PHIGH
Fig.3: PCI Clock timing
t
PVAL
t
PON
t
POFF
INPUT
Fig.4: PCI Bus Signals timing
Condition
Min.
30
11
11
1
2
2
2
-
7
10
12
0
0.5 V
DD3
0.4 V
0.3 V
t
PLOW
t
PCYC
1.5 V
t
PSU
-54-
Typ.
Max.
-
-
-
-
-
-
-
4
-
11
-
12
-
-
-
28
-
-
-
-
-
-
-
-
=10 pF
L
DD3
DD3
1.5 V
t
PH
1.5 V
February 3, 1999
Unit
ns
ns
ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
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