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YMF744B
4. AC Characteristics
4-1. Master Clock
Item
XI24 Cycle Time
XI24 High Time
XI24 Low Time
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V
4-2. Reset
(Fig.2)
Item
Reset Active Time after Power Stable
Power Stable to Reset Rising Edge
Reset Slew Rate
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, C
PVDD, LVDD,
VDD, CVDD
RST#
(Fig.1)
Symbol
t
XICYC
t
XIHIGH
t
XILOW
XI24
t
XIHIGH
Fig.1: XI24 Master Clock timing
Symbol
t
RST
t
RSTOFF
-
Fig.2: PCI Reset timing
Min.
Typ.
Max.
-
40.69
-
13
-
24
13
-
24
2.3 V
t
XILOW
t
XICYC
Min.
Typ.
1
-
10
-
50
-
3.0 V
t
RSTOFF
t
-53-
Unit
ns
ns
ns
1.65 V
1.0 V
Max.
Unit
-
ms
-
ms
-
mV/ns
=50 pF
L
RST
0.8 V
February 3, 1999
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