Circuit Description; Receive Signal Path; Sub-Audible Signaling (Decoder); Squelch Control - Vertex Standard VXR-7000 Service Manual

Receive Signal Path

Incoming RF from the RX antenna jack is delivered to the
RX Unit and passes through the protection diode D3001
(MA143) and a varactor-tuned band pass filter consisting of
coils L3002 and L3004, capacitors C3019, C3021, C3024,
C3027, and C3028, and diodes D3004 and D3008 (both
HVU350). Signals are then applied to the RF amplifier, Q3008
(2SC3357 . The amplified RF signal is applied through a var-
actor-tuned band pass filter consisting of coils L3009 and L3012,
capacitors C3053, C3054, C3059, C3060, and C3065, and di-
odes D3012 and D3013 (both HVU350) to the first mixer D3014
(GN2011-Q) along with the first local signal from the PLL
circuit.
The first local signal is generated between 114.6 MHz and
152.6 MHz by the RX VCO, which consists of FET Q3007
(2SK508 and varactor diodes D3005, D3006, D3009, and
D3010 (HVU350) according to the programmed receiving fre-
quency; the local signal then passes through buffer amplifier
Q3009 (2SC5226) and first local amplifier Q3011 (2SC3357)
to the first mixer D3014.
The 21.4 MHz first IF signal is applied to monolithic crys-
tal filters XF3001 and XF3002 (both 21M10B1: ±10 kHz B.W.)
which strip away unwanted mixer products, and the IF signal is
applied to the first IF amplifier Q3016 (2SC2620QB). The
amplified first IF signal is then delivered to the FM IF sub-
system IC Q3012 (TA31136FN), which contains the second
mixer, second local oscillator, limiter amplifier, noise amplifi-
er, and FM detector.
The second local oscillator signal, generated by the 20.945
MHz crystal X3002, produces the 455 kHz second IF signal
when mixed with the first IF signal within Q3021. The second
IF signal passes through ceramic filter CF3001 (CFWM455G:
±4.5 kHz B.W.) or CF3002 (CFWM455F: ±6.0 kHz B.W.)
which strips away all but the desired signal, and then passes
through the limiter amplifier within Q3021 to ceramic discrim-
inator CD3001 (CDB455C7), which removes any amplitude
variations in the 455 kHz IF signal before detection of speech.
The detected audio passes through the low pass filter, consist-
ing of R3067 and C3115, which rejects the 455 kHz IF compo-
nent, then delivers the audio to pin 12 of JP3001.
The audio signal from the RX Unit is delivered to the CNTL
Unit and passes through the audio amplifier Q4014-3
(NJM2902M) to the active high pass filter section of Q4024
(FX-805) which rejects the sub-audible frequency component.
The filtered audio signal is delivered to potentiometer VR4001,
which adjusts the audio sensitivity to compensate for audio level
variations, then passes through audio amplifier Q4014-2
(NJM2902M), audio switch Q4030 (NJU4066BM), a 20 dB
attenuator consisting of R4180 and R4211, and limiter amplifi-
er Q4018-2 (NJM2902M), to the electronic volume control
Q4029 (M51132FP), where the maximum deviation is set. The
audio signal subsequently passes through the a 3-section active
low pass filter consisting of Q4019-1/-2/-3 (NJM2902M) and

Circuit Description

audio amplifier Q4019-4 to J4008's pin 10, providing the re-
peater transmit audio.
A portion of the audio signal from the active high pass filter
section of Q4024 is de-emphasized by Q4020-1 (NJM2902M),
providing a flat audio response. The filtered audio then passes
through the active band pass filter Q4016 (NJM2902M) and
audio mute gate Q4038 (DTC323TK) to audio power amplifi-
er Q4043 (TDA2003H), providing up to 2 Watts of audio power
to the 8 Ω loudspeaker.

Sub-Audible Signaling (Decoder)

A portion of the audio signal from the audio amplifier
Q4014-1 passes through the active low pass filter at Q4014-2
and the low pass filtering section of Q4024 to separate the sub-
audible tones from the received audio signal. The sub-audible
tones are sent to the CTCSS/DCS decoder section of Q4024.
When a CTCSS tone or DCS code is received, the CTCSS or
DCS information is delivered to pin 20 of the Main CPU Q4012
from pin 4 of Q4024, which compares the CTCSS tone or DCS
code with the programmed tone or code data. If the received
CTCSS tone or DCS code matches the programmed tone or
code, pin 39 of the Main CPU Q4012 goes low, turning on the
squelch switch Q4036 (DTC323TK) and passing the received
audio signal to the audio power amplifier, Q4043.

Squelch Control

The squelch cir
cuit consists of noise amplifier Q3014
(2SC4116) and noise detector D3018 (MA143) on the RX
Unit, and control circuitry within main microprocessor Q4012
on the CNTL Unit.
When no carrier is received, noise at the output of the audio
detector stage of Q3012 is amplified by Q3014 (2SC4116GR),
and then rectified by D3018 (MA143) to provide a DC control
voltage for the squelch switch. The resulting DC voltage is de-
livered to pin 6 of JP3001.
The DC voltage from the RX Unit is delivered to the A-D
analog input port (pin 31) of the Main CPU Q4012
(HD64F3337YF16) on the CNTL Unit, which compares the
squelch threshold level to that which is memorized in EEPROM
Q4008 (NM93C86A or set by the front panel SQL control.
RX PLL and VCO Circuits
The r
eceiver's PLL circuitry consists of PLL subsystem
IC Q3001 (MB15A02PFV1) on the RX Unit, which contains
a reference oscillator/divider, serial-to-parallel data latch, pro-
grammable divider, phase comparator and a swallow counter.
Stability is obtained by a regulated 5 VDC supply via Q3021
(TA78L05) and the temperature-compensated temperature com-
pensated 14.4 MHz crystal oscillator X3001 via thermistor
TH3001 and TH3002.
The RX VCO, consisting of FET Q3007 and varactor di-
odes D3005, D3006, D3009, and D3010, oscillates between
114.6 MHz and 152.6 MHz according to the programmed re-
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