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ADVANCED CHIPSET SETUP
These setup functions are working mostly for Chipset (Intel 440BX). These op-
tions are used to change the Chipset's registers. Carefully change any default set-
ting, otherwise the system will run unstably.
Enabled will select predetermined optimal values of chipset
Configure SDRAM Timing by SPD >:
parameters. When
, chipset parameters return to setup information stored in CMOS.
Disabled
Used to specify the relative delay between row and column ad-
SDRAM RAS# to CAS Delay >:
dress strobe from SDRAM.
This option specifies the length of time for Row Address Strobe
SDRAM RAS# Precharge >:
from SDRAM to precharge.
Used to specify the CAS latency timing from SDRAM DRAM.
SDRAM CAS# Latency >:
Used to choose DRAM Integrity Mode; ECC/EC will enable the Error
DRAM Integrity Mode >:
Checking and Correction DRAM integrity mode.
Used to specify the timing for DRAM Refresh.
DRAM Refresh Rate >:
Used to specify the location of a memory hole in the CMOS RAM. This set-
Memory Hole >:
ting reserves 15 to 16 MB memory address space for ISA expansion cards that specifi-
cally require this setting. Memory from 15 MB and up will be unavailable to the system
because expansion cards can only access memory up to 16 MB.
Used to specify whether or not a caching of the video A000-BFFF
VGA Frame Buffer USWC >:
RAM is allowed.
will provide better system performance.
Enabled
AMI BIOS Setup Menus
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