Aborted Store That Hits The Data Cache May Mark Writeback Data As Dirty - Intel 80219 Specification Update

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Intel 80219 General Purpose PCI Processor
Core Errata
10.

Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty

Problem: When there is an aborted store that hits clean data in the data cache (data in an aligned four word
range, that has not been modified from the core, since it was last loaded in from memory or
cleaned), the data in the array is not modified (the store is blocked), but the dirty bit is set.
When the line is then aged out of the data cache or explicitly cleaned, the data in that four word
range is evicted to external memory, even though it has never been changed. In normal operation,
this is nothing more than an extra store on the bus, that writes the same data to memory as is
already there.
Here is the boundary condition where this might be visible:
1. a cache line is loaded into the cache at address A
2. another master externally modifies address A
3. a core store instruction attempts to modify A, hits the cache, aborts because of MMU
permissions, and is backed out of the cache. That line should not be marked dirty, but because
of this errata is marked as dirty.
4. the cache line at A then ages out or is explicitly cleaned. The original data from location A is
evicted to external memory, overwriting the data written by the external master.
This only happens when software is allowing an external master to modify memory, that is,
writeback or write-allocate in the page tables, and depending on the fact that the data is not 'dirty' in
the cache, to preclude the cached version from overwriting the external memory version. When
there are any semaphores or any other handshaking to prevent collisions on shared memory, this
should not be a problem.
Workaround: For this shared memory region, mark it as write-through memory in the page table. This prevents
the data from ever being written out as dirty.
Status: NoFix.
16 Specification Update