Intel 6300ESB ICH User Manual page 23

Processor with 800 mhz system bus, chipset and development kit
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Table 4.
Jumper Settings (Sheet 2 of 3)
Jumper Name
FSB Clock Frequency
(Host Clock Jumpers)
FORCEPR0 inject
STPCLK Inject
FORCEPR1 inject
CPU1 Present Override
BSEL Match Override
CPU1 VID Override
MCH SMBus Header
Intel
Controller Top Swap (FWH
Memory Swap)
®
Intel
Xeon™ Processor, Intel
Ref Des
BSEL1: J4H4
Override
BSEL0: J4J3
SMI Inject
J4H5
J4H6
J4J1
J4J2
J4J5
J4J7
CPU1 VID
J4K1
J4K2
J5D3
PLLS0
J5E112
®
6300ESB I/O
J5F1
PLLS1
J5F113
®
E7520 Chipset, Intel
Description/Settings
BSEL0
BSEL1
1-2
1-2
2-3
2-3
2-3
Open
Open
Open
Open
1-2
Inject SMI Signal
Do Not Install Jumper
Inject FORCEPR0 Signal
Do Not Install Jumper
Inject STPCLK Signal
Do Not Install Jumper
Inject FORCEPR1 Signal
Do Not Install Jumper
Override VRM disable if CPU1 is not present
1-2: Override
Open: Normal
Override VRM disable if BSELs do not match
1-2: Override
Open: Normal
1-2: VID[5]
3-4: VID[4]
5-6: VID[3]
7-8: VID[2]
9-10: VID[1]
11-12: VID[0]
Manual VID select
1-2: Manual select
Open: CPU select
Access to MCH SMbus
Do not install Jumper
1: MCH _SMBDAT
2. Ground
3. MCH_SMBCLK
See MCH Documentation for alternative Gear
Ratios for MCH FSB/Memory
Intel 6300ESB I/O Controller Top Swap
1-2: Top Swap
Open: Normal
See MCH Documentation for alternative Gear
Ratios for MCH FSB/Memory
®
6300ESB ICH Development Kit User's Manual
Jumpers and Headers
Default
Position
SPEED
Normal
RSVD
BSEL0: 1-2
BSEL1: 1-2
133 MHz
167 MHz
200 MHz
Open
Open
Open
Open
Open
Open
As
Required
Open
Open
Short
Open
Short
23

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E7520Xeon

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