Platform Resets; Platform Reset Diagram - Intel 6300ESB ICH User Manual

Processor with 800 mhz system bus, chipset and development kit
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5.3

Platform Resets

Figure 7
depicts the reset logic for the CRB. The Intel 6300ESB I/O Controller provides most of
the reset following assertion of power good and system reset. However, the glue logic within the
SIO is also used to buffer reset to PXH, MCH, FWH, and IDE.
Figure 7.

Platform Reset Diagram

SYS_RESET#
VRM_PWRGD
®
Intel
Xeon™ Processor, Intel
PCI 32
PCI-X
PCI-X
Port 80
Intel ®
6300ESB
I/O
Controller
Hub
SYS_PWRGD_3V3
®
E7520 Chipset, Intel
IDERST#
SIO
IDE
FWH
CPURST#
MCH
PXH_P PCIRST_N
PXH
PCI-E
®
6300ESB ICH Development Kit User's Manual
System Overview
CPU 0
CPU 1
ITP-700
PCI-X
PCI-X
PCI-X
2938-03
27

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