Pll Circuits; Power Supply Circuits - Icom IC-F3GT Service Manual

The signal output from the power detector circuit (D32, D33)
is applied to the differential amplifier (IC3a, pin 2), and the
"T4" signal from the expander (IC10, pin 11), controlled by
the CPU (IC8), is applied to the other input for reference.
When the driving current is increased, input voltage of the
differential amplifier (pin 2) will be increased. In such cases,
the differential amplifier output voltage (pin 1) is decreased
to reduce the driving current.
4-3 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the VCO circuit (Q7, Q8). The oscil-
lated signal is amplified at the buffer-amplifiers (Q6, Q5) and
then applied to the PLL IC (IC1, pin 2).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The entered
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the refer-
ence frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
A portion of the VCO signal is amplified at the buffer-ampli-
fier (Q4) and is then applied to the receive 1st mixer (Q13)
or transmit buffer-amplifier circuit (Q3) via the T/R switching
diode (D3, D4).
• PLL circuit
"DEV" signal from the
D/A convertor (IC10, pin 22)
when transmitting
VCO circuit
Q7, Q8
Loop
filter
8
30.6 MHz signal
to the FM IF IC
17
2

4-4 POWER SUPPLY CIRCUITS

VOLTAGE LINE
LINE
HV The voltage from the attached battery pack.
The same voltage as the HV line (battery volt-
VCC age) which is controlled by the power swtich
([VOL] control).
Common 5 V converted from the VCC line by the
reference regulator circuit (IC6). The output volt-
5V
age is applied to the 5 V regulator circuit (Q18,
Q19).
5 V for transmitter circuits regulated by the T5
T5
regulator circuit (Q22).
5 V for receiver circuits regulated by the R5 reg-
R5
ulator circuit (Q21).
Common 5 V converted from the VCC line by the
S5
S5 regulator circuit (Q18, Q19).
The same voltage as the 5V line for the optional
OPT HM-46L, EM-71 or HS-51 through a resistor
(R132).
The same voltage as the 5V line which is regu-
lated by +5 V CPU regulator circuit (IC6). The
CPU5
voltage is applied to the reset circuit (IC11) and
CPU (IC8).
Buffer Buffer
Q6 Q4
Buffer
Q5
Phase Programmable
detector counter
Programmable
Shift register
divider
16
X1
15.3 MHz
4 - 4
DESCRIPTION
D3
to transmitter circuit
to 1st mixer circuit
D4
2
Prescaler
3
PLST
4
SCK
5
SO