Port Allocations - Icom IC-F3GT Service Manual

4-5 PORT ALLOCATIONS

4-5-1 CPU (IC8)
Pin Port
number name
1 VIN Input port for battely voltage detection.
9 RESET Input port for RESET signal.
Outputs reference oscillator for the
11 CSIFT
CPU control signal.
Outputs clock signal to the PLL IC
12 SCK
(IC1), EEPROM (IC7), etc.
• Outputs strobe signals to the
expander IC (IC10, pin 6).
15 DAST
• Input port for the initial version sig-
nal.
16 CLIN Input port for the cloning signal.
17 CLOUT Outputs the cloning signal.
Outputs strobe signals to the PLL IC
18 PLST
(IC1, pin 3).
19 NOIS Input for for noise signals (pulse type).
Outputs BUSY detection.
21 BUSY
Low: The channel is busy.
26, 36, Input port for the optional unit detec-
OPV1–3
37 tion signal from J5.
Outputs Wide/Narrow mode control
38 NWC signal.
High: Wide mode is selected.
KR3– Output ports for key matrix.
44–47
KR0 Low: When the key is pushed.
• Outputs RX mute control signal.
49 RMUT • Input port for the RX mute signal
from optional units.
• Output TX mute control signal.
50 MMUT • Input port for the TX mute signal
from optional units.
Outputs low-pass filter cut-off frequen-
51 DUSE cy control signal when DTCS is acti-
vated.
Outputs S5 regulator control signal.
52 S5C
Low: While power is ON.
Outputs R5 regulator control signal.
53 R5C
Low: While receiving.
Outputs T5 regulator control signal.
54 T5C
Low: While transmitting.
Outputs APC circuit control signal.
55 TXC
High: While transmitting.
Outputs control signal for the regulator
56 AFON circuit of AF power amplifier.
High: When squelch is open, etc.
Outputs LCD backlight control signal.
57 LIGT
High: Lights ON.
Outputs EEPROM (IC7, pin 6) clock
58 ESCK
signal.
I/O port for data signals from/to EEP-
59 ESDA
ROM (IC7, pin 5)
Description
CPU (IC8)–continued
Pin Port
number name
63 UNLK
90 MTONE
91 DTMF
94 CTCIN
95 PTT0
96 BDET
97 REM0
98 SD
99 LVIN
100 TEMP
4-5-2 OUTPUT EXPANDER IC (IC10)
Pin Port
number name
2, 3,
T1–T4
10, 11
6 DAST
7 SCK
4 - 5
Description
Input port for unlock signal.
High: PLL is unlocked.
Low: PLL is locked.
Output port for:
Beep audio while receiving.
2/5-tone signals while transmitting.
Outputs DTMF tone signal while trans-
mitting.
CTCSS/DTCS signals input port for
decording.
Input port for the [PTT] switch.
High: While [PTT] switch is pushed.
Input port for the battery's type detec-
tion.
Input port for the remote-control signal
from external MIC (HM-75).
Input port for the RSSI detection.
Input port for the PLL lock voltage.
Input port for the transceiver's internal
temperature detection.
Description
Output tunable bandpass filter control
signals.
Input port for strobe signal from the
CPU (IC8, pin 15).
Input port for clock signal from the
CPU (IC8, pin 12).