Table of Contents
Advertisement
Table 4-P.
Delay Times for
Programmable
Buffered Interface
Figure 4-6.
Board Layout
for Programmable
Buffered Interface
SW1 Position
(O)pen (C)losed
1
2
3
4
* *
C
C
C
C
O C
C
C
C
O C
C
O O C
C
C
C
O C
O C
O C
C
O O C
O O O C
C
C
C
O
O C
C
O
C
O C
O
O O C
O
C
C
O O
O C
O O
C
O O O
O O O O
* * Default setting as shipped
DSR
W15
W16
Test
GND
RSTBIAS
W17
W18
W19
W20
OFF
ON
KG
NORM
W6
W5
SHORT
W1
W14
W2
100 ohm
CHASSIS GND
W7
W8
W9
2240 Fiber Optic Modem
Delay Time
P53
20 ns
30 ns
40 ns
50 ns
60 ns
70 ns
80 ns
90 ns
100 ns
110 ns
120 ns
130 ns
140 ns
150 ns
160 ns
170 ns
Dl1
J3
INVERT
W10
KG OUT
W13
W12
W11
NORM
-6V
+/-6V
+6V
Sw1
79
Hide quick links:
Advertisement
Table of Contents
