Extra Clock Pins In Tail Circuit Application At Clock Source End - Canoga Perkins 2240 User Manual

Canoga Perkins
Customer's T1
CSU/DSU
NOTE 1: X equals the extra clock input pins on the enhanced interfaces.
"Extra clock" jumper would have to be ON at this 2240.
NOTE 2: Control lead crossovers are not shown for clarity.
NOTE 3: The 2240 in the diagram would be operating in Mode 7, with rate set to
match CSU / DSU speed. The 2240 at far end would be operating in
slave mode.
28
Enhanced 2240 with Extra Clock
PLL
RT TT FIFO CONTROL
WR
FIFO
RD SD DI
ST X FIFO CONTROL
RD
SD RD DO
RT
TX
OPTICS
R
FIBER
DO
W
DI OPTICAL
RX
Figure 2-5.
Extra Clock Pins
in Tail Circuit
Application at
Clock Source End