Zenith D60WLCD Series Service Manual page 43

FUNCTIONAL DESCRIPTION
1) Analog Channel
THS8083 contains 3 identical analog channels that are
independently programmable. Each channel consists of
a clamping circuit, a programmable gain amplifier and
an A/D converter.
Analog Channel Architecture
Reference
Level
CLP
Vin
PGA1
Cc
Bottom/mid
Reference
Level
8
Offset
DAC
Clamp
6
Control
PGA Gain
Control
2) Clamping Circuit
The purpose of clamping is to provide the input signal
with a known DC-value. Typically video signals will be
AC-coupled into the part. The signal needs to be level-
shifted to fall between the reference voltage
range(VREFB..VREFT) of the A/D. By supplying a
programmable clamp, the user can shift the input signal
with respect to the A/D range. This has the same effect
as keeping the input signal constant and applying
offset to both A/D reference voltages while keeping
the VREFT-VREFB difference equal. However no external
adjustments are needed with this implementation.
For video, the clamping circuit can only be active during
the non-active video portion of each line to avoid
changes in brightness along the line. Clamping is done
during the horizontal blanking interval, either on the
backporch of sync or during the sync tip (in the case
of a sync present on at least one of the video channels).
If HS is carried on a separate line, as is typically the
case for PC graphics, clamping is done during blanking.
D60WLCD - 923-03486
CIRCUIT DESCRIPTIONS
PGA2
ADC
Clamp
DAC
Since for RGB type inputs, the blanking level will corre-
spond to a low output code of the A/D, it makes sense
to center the clamp range around a (0) A/D output
code. In this way the user can either offset up or down
this level symmetrically around (0). If the clamping is
set such that the blanking level corresponds to a level
below (0), the A/D output is clipped at code 0.
Bottom-level clamping
CLIP 255
255
ADC OUTPUT
8
CODE RANGE
0
CLIP 0
CLP PULSE
influence of change in clamp codes on
A/D output, while keeping PGA gain setting
constant, in bottom-level clamp mode
Mid-level clamping
CLIP 255
255
ADC OUTPUT
CODE RANGE
0
CLIP 0
CLP PULSE
influence of change in clamp codes on
A/D output, while keeping PGA gain setting
constant, in bottom-level clamp mode
3-19
CLAMP CODE
=+63 =0 =-64
+63
0
63
-64
Vin
CLAMP CODE
=+63 =0 =-64
+63
0
63
-64
Vin
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