Pioneer DJM-1000 Service Manual page 153

5
No. Pin Name
TIMER 1
13 TOUT1/AXR0[4]/AXR1[11]
12 TINP1/AHCLKX0
TIMER0
18 TOUT0/AXR0[2]/AXR1[13]
17 TINP0/AXR0[3]/AXR1[12]
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
8 CLKS1/SCL1
36 CLKR1/AXR0[6]/AXR1[9]
33 CLKX1/AMUTE0
37 DR1/SDA1
32 DX1/AXR0[5]/AXR1[10]
38 FSR1/AXR0[7]/AXR1[8]
31 FSX1
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
28 CLKS0/AHCLKR0
19 CLKR0/ACLKR0
16 CLKX0/ACLKX0
27 DR0/AXR0[0]/AXR1[15]
20 DX0/AXR0[1]/AXR1[14]
24 FSR0/AFSR0
21 FSX0/AFSX0
INTER-INTEGRATED CIRCUIT 1 (I2C1)
8 CLKS1/SCL1
37 DR1/SDA1
INTER-INTEGRATED CIRCUIT 0 (I2C0)
41 SCL0
42 SDA0
GENERAL-PURPOSE INPUT/OUTPUT 0 (GP0)
174 HD15/GP0[15]
173 HD14/GP0[14]
172 HD13/GP0[13]
168 HD12/GP0[12]
167 HD11/GP0[11]
166 HD10/GP0[10]
165 HD9/GP0[9]
160 HD8/GP0[8]
7 GP0[7](EXT_INT7)
2 GP0[6](EXT_INT6)
GP0[5](EXT_INT5)/AMUTEIN0
6
GP0[4](EXT_INT4)/AMUTEIN1
1
5
6
I/O
Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z) or McASP1 TX/RX data pin 11
O
(I/O/Z).
I Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock (I/O/Z).
Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z) or McASP1 TX/RX data pin 13
O
(I/O/Z).
Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z) or McASP1 TX/RX data pin 12
I
(I/O/Z).
I McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z).
McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z) or McASP1 TX/RX
I/O/Z
data pin 9 (I/O/Z).
I/O/Z McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).
I McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).
McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z) or McASP1 TX/RX
O/Z
data pin 10 (I/O/Z).
McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z) or McASP1
I/O/Z
TX/RX data pin 8 (I/O/Z).
I/O/Z McBSP1 transmit frame sync
McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-
I
frequency master clock (I/O/Z).
I/O/Z McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).
I/O/Z McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z).
McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z) or McASP1 TX/RX data
I
pin 15 (I/O/Z).
McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z) or McASP1 TX/RX
O/Z
data pin 14 (I/O/Z).
McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock
I/O/Z
(LRCLK) (I/O/Z).
McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock
I/O/Z
(LRCLK) (I/O/Z).
I/O/Z McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z).
I/O/Z McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).
I/O/Z I2C0 clock
I/O/Z I2C0 data
I/O/Z Host-port data pin 15 (I/O/Z) [ default] or this pin can be programmed as a GP0 15 pin (I/O/Z).
I/O/Z
I/O/Z
Host-port data pins (I/O/Z) [default] or general-purpose input/output 0 pins (I/O/Z) and some
I/O/Z
function as boot configuration pins at reset.
I/O/Z
• Used for transfer of data, address, and control
I/O/Z
• Also controls initialization of DSP modes at reset via pullup/pulldown resistors
I/O/Z
I/O/Z
I/O/Z General-purpose input/output 0 pins (I/O/Z) which also function as external interrupts [default]
• Edge-driven
I/O/Z
• Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])
I/O/Z
GP0[4] and GP0[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0
I/O/Z
McASP0 mute input, respectively.
DJM-1000
6
7
Pin Function
7
8
A
B
C
D
E
F
153
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