Pioneer DJM-1000 Service Manual page 149

5
Pin Function
No. Pin Name
CLOCK/PLL CONFIGURATION
204 CLKIN
82 CLKOUT2/GP0[2]
184 CLKOUT3
205 CLKMODE0
202 PLLHV
178 OSCIN
179 OSCOUT
181 OSCVDD
180 OSCVSS
JTAG EMULATION
192 TMS
187 TDO
191 TDI
193 TCK
197 TRST
185 EMU1
186 EMU0
RESETS AND INTERRUPTS
176 RESET
175 NMI
7 GP0[7](EXT_INT7)
2 GP0[6](EXT_INT6)
GP0[5](EXT_INT5)/AMUTEIN0
6
GP0[4](EXT_INT4)/AMUTEIN1
1
HOST-PORT INTERFACE (HPI)
174 HD15/GP0[15]
173 HD14/GP0[14]
172 HD13/GP0[13]
168 HD12/GP0[12]
167 HD11/GP0[11]
166 HD10/GP0[10]
165 HD9/GP0[9]
160 HD8/GP0[8]
164 HD7/GP0[3]
HOST-PORT INTERFACE (HPI) (CONTINUED)
161 HD6/AHCLKR1
159 HD5/AHCLKX1
156 HD4/GP0[0]
154 HD3/AMUTE1
155 HD2/AFSX1
152 HD1/AXR0[8]/AXR1[7]
147 HD0/AXR0[11]/AXR1[4]
135 HINT/GP0[1]
144 HCNTL1/AXR0[14]/AXR1[1]
146 HCNTL0/AXR0[12]/AXR1[3]
139 HHWIL/AFSR1
143 HR/W/AXR0[15]/AXR1[0]
5
6
I/O
I Clock Input
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the PLL
O/Z
controller) or this pin can be programmed as GP0[2] pin (I/O/Z)
O Programmable clock output (OSC Divider internal signal from PLL controller)
I PLL input clock source select
A Analog power (3.3 V) for PLL
I Crystal oscillator Input (XI)
O Crystal oscillator output (XO)
S Power supply for crystal oscillator (1.2 V)
GND Ground for crystal oscillator
I JTAG test-port mode select
O/Z JTAG test-port data output
I JTAG test-port data input
I JTAG test-port clock
I JTAG test-port reset
I/O/Z
Emulation [1:0] pin
I/O/Z
I Device reset
I Nonmaskable interrupt
I/O/Z General-purpose input/output 0 pins (I/O/Z) which also function as external interrupts [default]
• Edge driven • Polarity independently selected via the External Interrupt Polarity Register bits
I/O/Z
(EXTPOL.[3:0]) GP0[4] and GP0[5] pins also function as AMUTEIN1 McASP1 mute input and
I/O/Z
AMUTEIN0 McASP0 mute input, respectively.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host-port data pins (I/O/Z) [default] or general-purpose input/output 0 pins (I/O/Z) and some
I/O/Z
function as boot configuration pins at reset.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z).
I/O/Z Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z).
Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP0 0 pin (I/O/Z) and
I/O/Z
is external interrupt capable through interrupt sharing.
I/O/Z Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z).
I/O/Z Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z).
Host-port data pin 1 (I/O/Z) [ default] or McASP0 TX/RX pin 8 (I/O/Z) or McASP1 TX/RX pin 7
I/O/Z
(I/O/Z).
Host-port data pin 0 (I/O/Z) [ default] or McASP0 TX/RX pin 11 (I/O/Z) or McASP1 TX/RX pin 4
I/O/Z
(I/O/Z).
O/Z Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP0 1 pin (I/O/Z).
Host control - selects between control, address, or data registers (I) [default] or McASP0 TX/RX
I
pin 14 (I/O/Z) or McASP1 TX/RX pin 1 (I/O/Z).
Host control - selects between control, address, or data registers (I) [default] or McASP0 TX/RX
I
pin 12 (I/O/Z) or McASP1 TX/RX pin 3 (I/O/Z).
Host half-word select - first or second half-word (not necessarily high or low order) (I) [default] or
I
McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z).
Host read or write select (I) [default] or McASP0 TX/RX pin 15 (I/O/Z) or McASP1 TX/RX pin 0 (I/O/Z).
I
DJM-1000
6
7
Pin Function
7
8
A
B
C
D
E
F
149
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