Zenith D52WLCD Series Service Manual page 23

The SYNC counter block counts the H sync signal input dur-
ing a certain period (.5ms) based on the clock obtained by
the internal VCO from the 4MHz crystal oscillator or ceramic
oscillator connected to EXTCLK/
XTAL (Pin 20), and returns these results to the H-NUMBER-
H/L status registers in 10 bits.
When the H sync signal is not input, H-NUMBER-H/L is 0 or 1.
For the V sync signal, the number of reference clock
(31.25kHz) pulses during 1 V cycle is counted, and these
results are returned to the V-NUMBER-H/L status registers in
10 bits.
When the V sync signal is not input, the count that matches
the frequency selected by VFREQ (I
NUMBER-H/L.
The SYNC count values and conversion formulas for each H
and V sync signal are shown below.
H sync signal fH [kHz]
15.73
31.5
33.75
45
Count value ([DEC] $ [HEX]) = fH # 5ms
V sync signal fV [kHz]
60
50
Count value ([DEC] $ [HEX]) = 1/(fV # 32ns)
D52WLCD
CIRCUIT DESCRIPTIONS
2 C bus) is returned to V-
Count value [HEX]
4F
9D
A8
E1
Count value [HEX]
208
271
23
Note that a 4MHz external clock can be input to
EXTCLK/XTAL (Pin 20) via a capacitor by setting CLK_SEL
(I 2 C bus).
A dummy sync can be output by setting SELDUM (I
Select the dummy sync frequency with HFREQ and VFREQ(
I 2 C bus).
However, note that when the dummy sync is selected, the
SYNC counter does not operate even if H and V sync signals
are input.
3) Notes on Operation
• Processing for unused pins
OPEN : Pins 1 to 3, 7, 8, 33 to 35, 38, 39, 41 to 43, 46 and
47
Connected to GND via a capacitor and resistor: Pins 4, 5,
10, 11, 36, 37, 44 and 45 (See each H and V input and the
Application Circuit.)
This is to prevent SYNC counter misoperation.
• Input the H and V inputs at sufficiently low impedance.
• Internal clamp timing
The internally generated clamp pulse follows the timings T1
and T2 shown below. Input H_IN and Sync on Y/Sync on
Green so that the clamp pulse does not overlap the video
interval to prevent clamping error.
2 C bus).
CIRCUITS