Ic Information - Pioneer DJM-800 Service Manual

1

7.4 IC INFORMATION

DYW1757(HD64F2377) : (DSP ASSY : IC 1)
• Microcomputer
A
Pin Function
No. Mark Pin Name
1 MD2 MD2
2 VSS VSS
3 P80 MUTE
4 VCC VCC
5 A0 A0
6 A1 A1
7 A2 A2
B
8 A3 A3
9 A4 A4
10 VSS VSS
11 A5 A5
12 A6 A6
13 A7 A7
14 A8 A8
15 A9 A9
16 A10 A10
17 A11 A11
C
18 VSS VSS
19 PB4 DIGIANA1
20 PB5 DIGIANA2
21 PB6 DIGIANA3
22 PB7 DIGIANA4
23 PA0 XDONE
24 PA1 XPGM
25 VSS VSS
26 PA2 DSP_RESET
27 PA3 FPGA_RESET
28 PA4 DIGIANA_SEL1
D
29 PA5 DIGIANA_SEL2
30 PA6 DIGIANA_SEL3
31 PA7 DIGIANA_SEL4
32 EMLE EMLE
33 TXD3 MIDI_TXD
34 P82 SIO_SEL0
35 PH0 SIO_SEL1
36 PH1 SIO_SEL2
37 PH2 SIO_SEL3
38 PH3 SIO_SEL4
E
39 WDTOVFn EMU_03
40 NMI NMI
41 VCC VCC
42 P10 SW_MAT0
43 P11 SW_MAT1
44 P12 SW_MAT2
45 P13 SW_MAT3
46 P14 SW_MAT4
47 P15 SW_MAT5
48 P16 SW_MAT6
F
152
1
2
I/O
I Mode pin 2 NOR: Mode 4 At rewriting: Mode 3
I GND
O MUTE signal 0: Mute ON, 1: Mute OFF
I Power supply
O Address bus output A0
O Address bus output A1
O Address bus output A2
O Address bus output A3
O Address bus output A4
I GND
O Address bus output A5
O Address bus output A6
O Address bus output A7
O Address bus output A8
O Address bus output A9
O Address bus output A10
O Address bus output A11
I GND
I CH1 Digital <-> Analog SW
I CH2 Digital <-> Analog SW H : Digital, L : Analog
I CH3 Digital <-> Analog SW H : Digital, L : Analog
I CH4 Digital <-> Analog SW H : Digital, L : Analog
I FPGA program ready H : Digital, L : Analog
O FPGA program clear
I GND
O RESET OUT H : Release of RESET, L : RESET
O RESET OUT H : Release of RESET, L : RESET
O CH1 input select 0: Analog side 1, 1: Digital side 1
O CH2 input select 0: Analog side 2, 1: Digital side 2
O CH3 input select 0: Analog side 3, 1: Digital side 3
O CH4 input select 0: Analog side 4, 1: Digital side 4
I Emulator enable pin Set to L level at normal operation. GND by 1k.
O MIDI TXD send only
O SIO port select 0 FPGA, DAC, selection (at power on) H : FPGA, L : DAC
O SIO port select 1 DIT selection L : DIT
O SIO port select 2 EEPROM selection
O FPGA_SIO0 DIR (CH1,CH3) selection L : DIR
O FPGA_SIO1 DIR (CH2,CH4) selection L : DIR
O Overflow output of the watch dock timer for H8JTAG emulator
I Nonmaskable interrupt L level fixing
I Power supply
I KEY matrix b0 input
I KEY matrix b1 input
I KEY matrix b2 input
I KEY matrix b3 input
I KEY matrix b4 input
I KEY matrix b5 input
I KEY matrix b6 input
DJM-800
2
3
Pin Function
3
4
4