Processor 7/7 - Clevo P170EM Service Manual

Schematic Diagrams

Processor 7/7

Sheet 9 of 61
Processor 7/7
B - 10 Processor 7/7
Ivy Bridge Processor 7/7 ( RESERVED )
CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2 1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG2 R83 *1K_04
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
D04
CFG4 Add net PANEL_SEL
R81 1K_04
PANEL_SEL 23
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5] 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG5 R77 *1K_04
CFG6 R74 *1K_04
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
CFG7
0: PEG Wait for BIOS for training
CFG7
R73 *1K_04
U32E
AH27
VCC_DIE_SENSE
CFG0 AK28 AH26
CFG[0] VSS_DIE_SENSE
AK29
CFG[1]
CFG2 AL26
CFG[2]
AL27
CFG[3]
CFG4 AK26 L7
CFG[4] RSVD28
CFG5 AL29 AG7
CFG[5] RSVD29
CFG6 AL30 AE7
CFG[6] RSVD30
CFG7 AM31 AK2
CFG[7] RSVD31
AM32
CFG[8]
AM30 W8
CFG[9] RSVD32
AM28
CFG[10]
AM26
AN28 CFG[11] AT26
AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
AM27 CFG[14] RSVD35
AK31 CFG[15]
AN29 CFG[16]
CFG[17]
T8
RSVD37
J16
RSVD38
AJ31 H16
H_CPU_RSVD1
VAXG_VAL_SENSE RSVD39
H_CPU_RSVD2 AH31 G16
VSSAXG_VAL_SENSE RSVD40
AJ33
H_CPU_RSVD3
VCC_VAL_SENSE
H_CPU_RSVD4 AH33
VSS_VAL_SENSE
AJ26 AR35
RSVD5 RSVD_NCTF41
AT34
RSVD_NCTF42
AT33
RSVD_NCTF43
AP35
RSVD_NCTF44
AR34
RSVD_NCTF45
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24 B34
RSVD11 RSVD_NCTF46
G25 A33
RSVD12 RSVD_NCTF47
G24 A34
RSVD13 RSVD_NCTF48
E23 B35
RSVD14 RSVD_NCTF49
D23 C35
C30 RSVD15 RSVD_NCTF50
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
A30 RSVD21 RSVD52
RSVD22
C29
RSVD23
AN35
BCLK_ITP
J20 AM35
RSVD24 BCLK_ITP#
B18
RSVD25
J15 AT2
RSVD27 RSVD_NCTF56
AT1
RSVD_NCTF57
AR1
RSVD_NCTF58
B1
KEY
Iv y Bridge_rPGA_2DPC_Rev 0p61