Processor 2/7 - Clevo P170EM Service Manual

Processor 2/7

Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
PROC_SELET
25 H_SNB_IVB#
SKTOCC#
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up H_CATERR#
resistor to 1.05VS_VTT .
R50 *10mil_short
25,35 H_PECI
R52 56_1%_04
45 H_PROCHOT#
R51 *10mil_short
25 H_THRMTRIP#
R302 *10mil_short
22 H_PM_SY NC
R41 *10mil_short
25 H_CPUPWRGD
PMSYS_PWRGD_BUF
R521 130_1%_04
Buffered reset to CPU
3.3VS 1.05VS_VTT
R97
R39
10K_04
3 75_04
D
2,14,24 PLT_RST#
5 G R40 43_1%_04 BUF_CPU_RST#
S Q37B
6 4 MTDN7002ZHS6R
D
R38 *1.5K_1%_04
R511 2 G Q37A
S MTDN7002ZHS6R
100K_04 1
C60
68P_50V_NPO_04
H_PROCHOT#
Q6
G
C82
35 H_PROCHOT#_EC
MTN7002ZHS3
47P_50V_NPO_04
R34
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
U32B
BCLK
C26
PROC_SELECT# BCLK#
AN34
SKTOCC#
DPLL_REF_CLK
DPLL_REF_CLK#
AL33
CATERR#
AN33
PECI SM_DRAMRST#
H_PROCHOT#_D AL32
PROCHOT# SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
AN32
THERMTRIP#
PRDY #
PREQ#
AM34
PM_SY NC TRST#
H_CPUPWRGD_R AP33
UNCOREPWRGOOD
DBR#
VDDPWRGOOD_R V8
SM_DRAMPWROK
BPM#[0]
BPM#[1]
AR33 BPM#[2]
BUF_CPU_RST#
RESET# BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
Iv y Bridge_rPGA_2DPC_Rev 0p61
S3 circuit:- DRAM PWR GOOD logic
3.3V 3.3V
R48
C306
*750_1%_04
R196 R199
1.5VS_CPU
1
22 PM_DRAM_PWRGD
4
2
22,44 1.8VS_PWRGD
U18
*MC74VHC1G08DFT1G
R193 0_04
G
41,42,43,44 SUSB
PU/PD for JTAG signals
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO_R
XDP_TCLK
XDP_TRST#
A28
CLK_EXP_P 21
A27
CLK_EXP_N 21
A16 XDP_DBR_R
CLK_DP_P 21
A15
CLK_DP_N 21
DDR3 Compensation Signals
R8
CPUDRAMRST#
SM_RCOMP_0
SM_RCOMP_1
AK1 SM_RCOMP_0
A5 SM_RCOMP_1 SM_RCOMP_2
A4 SM_RCOMP_2
AP29 XDP_PRDY #
AP27 XDP_PREQ#
Processor Pullups/Pull downs
AR26
XDP_TCLK
TCK AR27
XDP_TMS
TMS
AP30
XDP_TRST#
AR28 XDP_TDI_R H_PROCHOT#
TDI
AP26 XDP_TDO_R
TDO
H_CPUPWRGD_R
AL35
XDP_DBR_R P150HM_D04A
TRACE WIDTH 10MIL, LENGTH <500MILS
AT28
AR29
AR30
AT30
AP32
AR31
AT31
S3 circuit:- DRAM_RST# to memory
AR32
should be high during S3
R327 *0_04
BSS138 ( VGS 1.5V )
Q24
MTN7002ZHS3
CPUDRAMRST# S D
R331
R328 1K_04
4.99K_1%_04
R322
200_1%_04
C494
PMSY S_PWRGD_BUF 0.047u_10V_X7R_04
R325
*39_04
3.3VS 2,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,33,34,35,36,37,38,41,45,48
3.3V 3,7,15,20,21,22,24,25,26,27,30,31,33,37,38,41,43,44
1.5V 7,10,11,12,13,27,31,41,43
1.5VS_CPU 7,41
Q13
1.05VS_VTT 3,6,25,26,27,44,45,48
*MTN7002ZHS3
Schematic Diagrams
1.05VS_VTT
R82 51_04
R76 51_04
R84 *51_04
R308 51_04
R309 51_04
R67 51_04
3.3VS
1K_04 R301
R409 140_1%_04
R333 25.5_1%_04
R334 200_1%_04
Sheet 4 of 61
Processor 2/7
1.05VS_VTT
62_04 R42
10K_1%_04 R49
C568 0.1u_16V_Y 5V_04
1.5V
R329
1K_04
DDR3_DRAMRST# 10,11,12,13
DRAMRST_CNTRL 7,21
Processor 2/7 B - 5