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9.0 Electrical Specifications
Typical for 25 DegC unless otherwise specified.
Analog input section
A/D converter type
Resolution
Programmable ranges
A/D pacing
Data transfer
Bust mode
Polarity
Number of channels
Interrupts
Interrupt enable
A/D conversion time
Throughput
Differential Linearity error (Bipolar)
Integral Linearity error (Bipolar)
Differential Linearity error (Unipolar)
Integral Linearity error (Unipolar)
Gain Error
No missing codes guaranteed
Gain drift (A/D specs)
Zero drift (A/D specs)
Input leakage current (@25 Deg C)
Input impedance
Absolute maximum input voltage
A/D Triggering Modes
1
Integral linearity for 1.25V bipolar is specified at +/- 3LSB max
2
Integral linearity for 1.25V unipolar is specified at +/- 3LSB max
AD976ABN
16 bits
±10V, ±5V, ±2.5V, ±1.25V, 0 - 10V, 0 - 5V, 0 - 2.5V, 0 - 1.25V
Programmable: internal counter or external source
From 512 sample FIFO via REPINSW, int, software polled
Programmable option at 5us samples intervals during burst
Unipolar/Bipolar SW selectable
8 differential or 16 single-ended, SW selectable
INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable
5µs
200KHz min
±1 LSB
1
±1.5 LSB
±1 LSB
2
±1.5 LSB
±10V, 0-10V Ranges:
±5V, 0-5V Ranges:
±2.5V, 0-2.5V Ranges:
±1.25,V 0-1.25V Ranges: 22.5ppm typical, 45ppm Max
16 bits
±20ppm/°C, all ranges
±10ppm/°C, all ranges
200nA
Min 10Meg Ohms
±15V
Digital:
SW configurable for Edge (triggered) or level-activated (gated).
Programmable polarity (rising/falling edge trigger, high/low gate).
Analog:
SW configurable for above/below reference, in/out window and
hysteresis.
Programmable polarity (rising/falling edge trigger, high/low gate).
Trigger levels set by DAC0 and/or DAC1.
Pre-trigger:
Unlimited pre- and post-trigger samples. Total # of samples must
be > 256. Compatible with both Digital and Analog trigger
options.
Page 33
PCI-DAS1602/16
22.5ppm Max
22.5ppm Max
22.5ppm Max
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