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BADR2 + 2 ADC FIFO Clear register. A Write-only register. A write to this address location
clears the ADC FIFO. Data is don't care. The ADC FIFO should be cleared before all new
ADC operations.
8.4 BADR3
The I/O Region defined by BADR3 contains data and control registers for the ADC Pacer, DAC
Pacer, Pre/Post-Trigger Counters and High-Drive Digital I/O bytes. The PCI-DAS1602/16 has
two 8254 counter/timer devices. These are referred to as 8254A and 8254B and are assigned as
shown below:
Device
8254A
8254A
8254A
8254B
8254B
8254B
All reads/writes to BADR3 are byte operations.
8.4.1 ADC Pacer Clock Data And Control Registers
8254A COUNTER 0 DATA - ADC RESIDUAL SAMPLE COUNTER
BADR3 + 0
READ/WRITE
7
6
D7
D6
Counter 0 is used to stop the acquisition when the desired number of samples have been
gathered. It is gated on when a 'residual' number of conversions remain. Counter 0 will be
enabled by use of the ARM bit (BADR1 + 4).
Counter 0 is to operated in Mode 0.
8254A COUNTER 1 DATA - ADC PACER DIVIDER LOWER
BADR3 + 1
READ/WRITE
7
6
D7
D6
8254A COUNTER 2 DATA - ADC PACER DIVIDER UPPER
Counter #
0
ADC Post-Trigger Sample Counter
1
ADC Pacer Lower Divider
2
ADC Pacer Upper Divider
0
ADC Pre-Trigger Index/UserCounter
1
DAC Pacer Lower Divider
2
DAC Pacer Upper Divider
5
4
D5
D4
5
4
D5
D4
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Function
2
3
D3
D2
2
3
D3
D2
1
0
D1
D0
1
0
D1
D0
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