Table of Contents
Advertisement
ADNEI
Status bit of ADC FIFO Not-Empty interrupt. Used to indicate ADC conversion complete in
single conversion applications.
1 = Indicates an ADC FIFO Not-Empty interrupt has been latched and that one data word may be
read from the FIFO. 0 = Indicates an ADC FIFO Not-Empty interrupt has not occurred. FIFO
has been cleared, read until empty or ADC conversion still in progress.
ADNE
Real-time status bit of ADC FIFO Not-Empty status signal.
1 = Indicates ADC FIFO has at least one word to be read. 0 = Indicates ADC FIFO is empty.
LADFUL
Status bit of ADC FIFO FULL status. This bit is latched.
1 = Indicates the ADC FIFO has exceeded full state. Data may have been lost. 0 = Indicates
non-overflow condition of ADC FIFO.
DAEMI
Status bit of DAC FIFO Empty interrupt. Used to indicate that a FIFO'd DAC Operation has
completed.
1 = DAC FIFO Empty interrupt condition has occurred. 0 = DAC FIFO Empty interrupt condi-
tion has not occurred.
8.2.2 ADC Channel MUX And Control Register
BADR1 + 2
This register sets channel mux HI/LO limits, ADC gain, offset and pacer source.
A Read/Write register.
WRITE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
ADPS1
ADPS0
UNIBIP
SEDIFF
GS1
GS0
CHH8
CHH4
CHH2
CHH1
CHL8
CHL4
CHL2
CHL1
CHL8-CHL1,
CHH8-CHH1
When these bits are written, the analog input multiplexers are set to the channel specified by
CHL8-CHL1. After each conversion, the input multiplexers increment to the next channel,
reloading to the "CHL" start channel after the "CHH" stop channel is reached. LO and HI
channels are the decode of the 4-bit binary patterns.
GS[1:0]
These bits determine the ADC range as indicated below:
Page 16
Advertisement
Table of Contents
