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Note: For ADPS[1:0] = 00 case, SW conversions are initiated via a word write to BADR2 + 0.
Data is 'don't care.'
READ
15
14
13
12
-
EOC
-
EOC
Real-time, non-latched status of ADC End-of-Conversion signal.
1 = ADC DONE
0 = ADC BUSY
8.2.3 Trigger Control/Status Register
BADR1 + 4
This register provides control bits for all ADC trigger modes. A Read/Write register.
WRITE
15
14
13
12
-
-
C0SRC
FFM0
TS[1:0]
These bits select one-of-three possible ADC Trigger Sources:
Note: TS[1:0] should be set to 0 while setting up Pacer source and count values.
TGPOL
This bit sets the polarity for the external trigger/gate. Internally, the ADC is triggered on a rising
edge or gated on with an active high signal. Use TGPOL to condition external trigger/gate for
proper polarity.
1 = External trigger/gate input inverted.
0 = External trigger/gate input not inverted.
TGSEL
11
10
9
-
-
-
-
11
10
9
ARM
HMODE
CHI_EN
TS1
TS0
0
0
1
1
8
7
6
-
-
-
8
7
6
CLO_EN
XTRCL
PRTRG
BURSTE
Source
0
Disabled
1
SW Trigger
0
External (Digital)
1
External (Analog)
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5
4
3
2
-
-
-
-
5
4
3
2
TGEN
TGSEL
TGPOL
1
0
-
-
1
0
TS1
TS0
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