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CSRC[2:0]
These bits select the different calibration sources available to the ADC front end.
CALEN
This bit is used to enable Cal Mode.
1 = Selected Cal Source, CSRC[2:0], is fed into Analog Channel 0.
0 = Analog Channel 0 functions as normal input.
SDI
Serial Data In. This bit is used to set serial address/data stream for the DAC8800 TrimDac and
8402 digital potentiometer. Used in conjunction with SEL8800 and SEL8402 bits.
8.2.5 DAC Control/Status Register
BADR1 + 8
This register selects the DAC gain/range, Pacer source, trigger and High-Speed Modes. In
addition, DAC FIFO status information is available. This is a Read/Write register.
WRITE
15
14
13
12
-
-
-
LDAEMCL
This is a Write-clear bit to reset the latched EMPTY status flag of the DAC FIFO.
1 = Reset Empty Flag
0 = No Effect.
DACEN
CSRC2
CSRC1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
11
10
9
-
DAC1R1
DAC1R0
DAC0R1
CSRC0
Cal Source
0
1
0
1
0
1
0
VDAC0
1
VDAC1
8
7
6
5
DAC0R0
-
HS1
HS0
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AGND
7.0V
3.5V
1.75V
0.875V
-10.0V
4
3
2
DAPS1
DAPS0
START
1
0
DACEN
LDAEMCL
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