Sas Backplane; I/O Subsystem; Pcie Mps Optimization - HP Integrity BL860c User's & Service Manual

Figure 2 SAS Disk Drive Slots
For the location of the SAS disk LEDs, see

SAS Backplane

The SAS disk backplane supports two small form factor (SFF) hard disk drives. The backplane
supports hot-plugging a single SAS drive at a time. The activity LEDs and drive present LEDs shall
be controlled by a preprogrammed system-on-chip (PSOC). The system board hosts the SAS
controller, and supplies 12 V, 5 V, and 3.3 V standby power to the backplane. The backplane is
designed as a field-replaceable unit (FRU).
The SAS backplane is connected to the system board with a right angle connector. This connector
is specifically designed for high-speed differential applications, and supports server speeds
exceeding 5 Gigabits per second. Power, Sense, and I
as well as the SAS differential pairs and SGPIO signals.

I/O Subsystem

The I/O subsystem is composed of embedded core I/O, and up to three mezzanine cards. The
server blade supports one Type I and two Type II mezzanine cards (with PCI express links that
serves as a bridge between the zx2 ropes links and PCIe). The server blade does not support PCI
Hot Plug (PHP).
Memory controllers are used as the ropes to the PCI bridge for the system board fast and slow
core I/O. The server blade uses two memory controllers to interface with the Core LAN and SAS.
The memory controllers run at 33 MHz and interface with the manageability, USB, and graphics
through the serial, USB, and video (SUV) cable. The serial, USB, and video are provided through
the PCI devices attached to logical rope 0.

PCIe MPS Optimization

For PCIe-based systems, each PCIe device has a configurable maximum payload size (MPS)
parameter. Larger MPS values can enable the optimization to gain higher performance. MPS
Optimization is supported on PCIe systems running HP-UX, Open VMS, and Linux. System firmware
level greater than 01.01 performs an optimization during boot time to set the MPS value to the
largest size supported by the PCIe root port and the devices below it.
The default server state is optimization disabled. When disabled, system firmware sets MPS to the
minimum value on each PCIe device.
The info io command displays the current PCIe MPS optimization setting. See
16 Overview
Figure 5.
2
C signals are routed through this connector
Table 31 (page 153).