Advanced Chipset Setup - ECS L4S8M10 Manual

Small Logo (EPA) Show (Disabled)
Enables or disables the display of the EPA logo during boot.

Advanced Chipset Setup

The parameters in this screen are for system designers, service personnel,
and technically competent users only. Do not reset these values unless you
understand the consequences of your changes.
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Clock/Timing Control
AGP & P2P Bridge Control
Prefetch Caching
System BIOS Cacheable
Video RAM Cacheable
Memory Hole at 15M-16M
↑ ↓ → ← : Move
Enter : Select
F5:Previous Values
DRAM Clock/Timing Control
Scroll to this item and press <Enter> to view the following screen:
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Control
x DRAM CAS Latency
x RAS Active Time (tRAS)
x RAS Precharge Time (tRP)
x RAS to CAS Delay (tRCD)
DRAM Addr/Cmd Rate
↑ ↓ → ← : Move
Enter : Select
F5:Previous Values
DRAM Timing Control (By SPD)
Enables you to select the CAS latency time in HCLKs of 2, 2.5, or 3. The
value is set at the factory depending on the DRAM installed. Do not change
the values in this field unless you change specifications of the installed DRAM
or the installed CPU.
Advanced Chipset Features
[Press Enter]
[Press Enter]
[Disabled]
[Disabled]
[Disabled]
[Disabled]
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults
DRAM Clock/Timing Control
[By SPD]
2.5T
6T
3T
3T
[Auto Mode]
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults
34
Item Help
Menu Level
F1:General Help
F7:Optimized Defaults
Item Help
Menu Level
F1:General Help
F7:Optimized Defaults