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Introduction
architecture enable significant performance improvement over existing mobile processors. The
processor's data prefetch logic fetches data to the L2 cache before L1 cache requests occurs,
resulting in reduced bus cycle penalties and improved performance.
The streaming SIMD extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.
The new packed double-precision floating-point instructions enhance performance for applications
that require greater range and precision, including scientific and engineering applications and
advanced 3-D geometry techniques, such as ray tracing.
The Pentium M processor's 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The
400-MHz FSB uses source-synchronous transfer (SST) of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced
Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling
technology with low power enhancements.
The processor features Enhanced Intel SpeedStep technology, which enables real-time dynamic
switching between multiple voltage and frequency points. This results in optimal performance
without compromising low power. The processor features the Auto Halt, Stop Grant, Deep Sleep,
and Deeper Sleep low power states.
The Pentium M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and
surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-
FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is
referred to as the mPGA479M socket.
Pentium M processors with CPU Signature = 06D8h will also include the Execute Disable Bit
capability. This feature combined with a support operating system allows memory to be marked as
executable or non executable. If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the
system. See the Intel
Intel will validate this feature only on Intel 915 Express chipset family based platforms and
recommends customers implement BIOS changes related to this feature, only on Intel 915 Express
chipset family based platforms.
Note: The term AGTL+ is used to refer to Assisted GTL+ signalling technology on some Intel processors.
8
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Architecture Software Developer's Manual for more detailed information.
Datasheet
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