Figures
2-1 Clock Control States................................................................................................................... 11
3-1 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#A)............................ 31
3-2 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#A) ................... 32
3-3 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#B)............................ 33
3-4 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#B) ................... 34
3-5 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#C) ........................... 35
3-6 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#C) ................... 36
3-7 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#D) ........................... 37
3-8 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#D) ................... 38
3-9 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#E)............................ 39
3-10 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#E) ................... 40
3-11 Active VCC and ICC Load Line .................................................................................................. 43
3-12 Deep Sleep VCC and ICC Load Line ......................................................................................... 44
4
Datasheet