Technical data of CPU 31xC
6.5 CPU 314C-2 PtP and CPU 314C-2 DP
Technical data
Data areas and their retentivity
Flag bits
Retentive memory
•
Default retentivity
•
Clock flag bits
Data blocks
Length
•
Local data per priority class
Blocks
Total
OBs
Length
•
Nesting depth
Per priority class
•
additional within an error OB
•
FBs
Length
•
FCs
Length
•
Address areas (I/O)
Total I/O address area
Distributed
•
I/O process image
Digital channels
of those local
•
Integrated channels
•
Analog channels
of those local
•
Integrated channels
•
Assembly
Racks
Modules per rack
Number of DP masters
Integrated
•
via CP
•
6-22
CPU 314C-2 PtP
CPU 314C-2 PtP
256 bytes
Configurable
MB0 to MB15
8 (1 byte per flag bit)
Max. 511
(DB 1 to DB 511)
max. 16 KB
max. 510 bytes
CPU 314C-2 PtP
1024 (DBs, FCs, FBs)
The maximum number of blocks that can be loaded may be reduced if you are
using another MMC.
See the Instruction List
max. 16 KB
8
4
Max. 512
(FB 0 to FB 511)
max. 16 KB
Max. 512
(FC 0 to FC 511)
max. 16 KB
CPU 314C-2 PtP
max. 1024 bytes/1024 bytes
(can be freely addressed)
None
128 bytes/128 bytes
Max. 1016
Max. 992
24 DI / 16 DO
Max. 253
Max. 248
4 + 1 AI / 2 AO
CPU 314C-2 PtP
Max. 4
max. 8; max. 7 in rack 3
No
Max. 1
CPU 314C-2 DP
CPU 314C-2 DP
CPU 314C-2 DP
CPU 314C-2 DP
max. 1024 bytes/1024 bytes
(can be freely addressed)
max. 1000 bytes
128 bytes/128 bytes
Max. 8192
Max. 992
24 DI / 16 DO
Max. 512
Max. 248
4 + 1 AI / 2 AO
CPU 314C-2 DP
1
Max. 1
CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05