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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
BUSMOD, CPUMOD: 00FF00H•D7, D6
Bus mode and CPU mode are set as shown in Table
5.2.6.2.
Table 5.2.6.2 Bus mode and CPU mode settings
Setting value
MCU/MPU
terminal
BUSMOD
CPUMOD
1 (MCU mode)
1
1
0
0
0 (MPU mode)
1
1
0
0
The single chip mode configuration is only possible
when this IC is used in the MCU mode. The single
chip mode setting is incompatible with the MPU
mode, since this mode does not utilize internal
ROM.
At initial reset, in the MCU mode the unit is set to
single chip (minimum) mode and in the MPU mode
the expansion (minimum) mode is used to select
the applicable mode.
CE0–CE2: 00FF00H•D0–D2
_____
Sets the CE output terminals being used.
When "1" is written:
When "0" is written:
Reading:
____
CE output is enabled when a "1" is written to
registers CE0–CE2 which correspond to the CE
output being used. A "0" written to any of the
____
registers disables CE signal output from that
terminal and it reverts to its alternate function as an
output port terminal (R30–R32).
At initial reset, register CE0 is set to "0" in the MCU
mode and in the MPU mode, "1" is set in the
register. Registers CE1–CE2 are always set to "0"
regardless of the MCU/MPU mode setting.
Note: To avoid a malfunction from an interrupt
generated before the bus configuration is
initialized, all interrupts including NMI are
masked until you write an optional value into
address "00FF00H".
SPP0–SPP7: 00FF01H
Sets the page address of stack area.
In single chip mode, set page address to "00H". In
expansion mode, it can be set to any value within
the range "00H"–"27H".
S1C88650 TECHNICAL MANUAL
Bus mode
mode
CPU
Expansion
Maximum
1
Minimum
0
Single
Maximum
1
chip
Minimum
0
Expansion
Maximum
1
Minimum
0
Maximum
1
Minimum
0
_____
CE output enable
_____
CE output disable
Valid
____
_____
Since a carry and borrow from/to the stack pointer
SP is not reflected in register SPP, the upper limit
on continuous use of the stack area is 64K bytes.
At initial reset, this register is set to "00H" (page 0).
Note: To avoid a malfunction from an interrupt
generated before the bus configuration is
initialized, all interrupts including NMI are
disabled, until you write an optional value
into "00FF01H" address. Furthermore, to
avoid generating an interrupt while the stack
area is being set, all interrupts including NMI
are disabled in one instruction execution
period after writing to address "00FF01H".
WT0–WT2: 00FF02H•D4–D6
How WAIT state settings are performed.
The number of WAIT states to be inserted based on
register settings is as shown in Table 5.2.6.3.
Table 5.2.6.3 Setting WAIT states
WT2
WT1
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
*
The length of one state is a 1/2 clock cycle.
At initial reset, this register is set to "0" (no wait).
EBR: 00FF02H•D7
________ ________
Sets the BREQ/BACK terminals function.
When "1" is written:
When "0" is written:
Reading:
________
________
How BREQ and BACK terminal functions are set.
Writing "1" to EBR enables BREQ/BACK input/
output. Writing "0" sets the BREQ terminal as input
port terminal K03 and the BACK terminal as output
port terminal R33.
At initial reset, EBR is set to "0" (BREQ/BACK
disabled).
EPSON
_____
WT0
Number of inserted states
1
14
0
12
1
10
0
8
1
6
0
4
1
2
0
No wait
________ ________
BREQ/BACK enabled
________ ________
BREQ/BACK disabled
Valid
________ ________
________
________
________ ________
_____
37
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