Contents
Figure 5.6 Protocol for the command execution without data transfer
Figure 5.7 Normal DMA data transfer
Figure 5.8 Data transfer timing
Figure 5.9 Single word DMA data transfer timing (mode 2)
Figure 5.10 Multiword DMA data transfer timing (mode 2)
Figure 5.11 Power on Reset Timing
Figure 6.1 Response to power-on
Figure 6.2 Response to hardware reset
Figure 6.3 Response to software reset
Figure 6.4 Response to diagnostic command
Figure 6.5 Address translation (example in CHS mode)
Figure 6.6 Address translation (example in LBA mode)
Figure 6.7 Sector slip processing
Figure 6.8 Alternate cylinder assignment
Figure 6.9 Data buffer configuration
Tables
xii
5-77
1-4
4-13
5-7
5-43
5-75
5-80
6-3
6-4
6-5
6-6
6-8
6-9
6-12
6-13
6-14
1-5
1-6
1-7
1-7
1-8
3-8
4-9
4-10
5-3
5-14
5-38
5-56
5-73
5-78
5-79
3-5
5-32
5-54
5-57
C141-E042-01EN