Fujitsu MHA2021AT Product Manual page 73

Interface
- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault
- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device
- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to
- Bit 2: Corrected Data (CORR) bit. This bit indicates that a correctable data
- Bit 1: Always 0.
- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the
(10) Command register (X'1F7')
The Command register contains a command code being sent to the device. After
this register is written, the command execution starts immediately.
Table 5.3 lists the executable commands and their command codes. This table
also lists the neccesary parameters for each command which are written to certain
registers before the Command register is written.
5-12
(write fault) condition has been detected.
If a write fault is detected during command execution, this bit is
latched and retained until the device accepts the next command or
reset.
heads are positioned over a track.
In the IDD, this bit is always set to 1 after the spin-up control is
completed.
transfer data of word unit or byte unit between the host system and the
device.
error was encountered and the error has been corrected. This condition
does not halt the data transfer.
previous command was being executed. The Error register indicates
the additional information of the cause for the error.
C141-E042-01EN