Fujitsu MHA2021AT Product Manual page 82

(3) READ DMA (X'C8' or X'C9')
This command operates similarly to the READ SECTOR(S) command except for
following events.
The data transfer starts at the timing of DMARQ signal assertion.
The device controls the assertion or negation timing of the DMARQ signal.
The device posts a status as the result of command execution only once at
completion of the data transfer.
When an error, such as an unrecoverable medium error, that the command
execution cannot be continued is detected, the data transfer is stopped without
transferring data of sectors after the erred sector. The device generates an
interrupt using the INTRQ signal and posts a status to the host system. The
format of the error information is the same as the READ SECTOR(S) command.
In LBA mode
The logical block address is specified using the start head No., start cylinder No.,
and first sector No. fields. At command completion, the logical block address of
the last sector and remaining number of sectors of which data was not transferred,
like in the CHS mode, are set.
The host system can select the DMA transfer mode by using the SET FEATURES
command.
1) Single word DMA transfer mode 0 to 2
2) Multiword DMA transfer mode 0 to 2
1F7
1F6
1F5
1F4
1F3
1F2
1F1
R = 0
R = 1
C141-E042-01EN
At command issuance (I/O registers setting contents)
(CM) 1 1
H
(DH) L
H
(CH) Start cylinder No. [MSB] / LBA
H
(CL) Start cylinder No. [LSB] / LBA
H
(SN) Start sector No. / LBA [LSB]
H
(SC) Transfer sector count
H
(FR) xx
H
with Retry
without Retry
0 0 1 0
DV Start head No. /LBA
[MSB]
5.3 Host Commands
0 R
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